Searched refs:MHz (Results 1 – 18 of 18) sorted by relevance
| /drivers/ata/ |
| D | pata_hpt37x.c | 823 static const int MHz[4] = { 33, 40, 50, 66 }; in hpt37x_init_one() local
988 f_low = (MHz[clock_slot] * 48) / MHz[dpll]; in hpt37x_init_one()
1022 MHz[clock_slot], MHz[dpll]); in hpt37x_init_one()
1037 chip_table->name, MHz[clock_slot]); in hpt37x_init_one()
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| /drivers/video/ |
| D | imsttfb.c | 438 setclkMHz(struct imstt_par *par, __u32 MHz) in setclkMHz() argument
454 if (x == MHz) in setclkMHz()
456 if (x > MHz) { in setclkMHz()
459 } else if (spilled && x < MHz) { in setclkMHz()
473 __u32 MHz, hes, heb, veb, htp, vtp; in compute_imstt_regvals_ibm() local
478 MHz = 30 /* .25 */ ; in compute_imstt_regvals_ibm()
482 MHz = 57 /* .27_ */ ; in compute_imstt_regvals_ibm()
486 MHz = 80; in compute_imstt_regvals_ibm()
490 MHz = 101 /* .6_ */ ; in compute_imstt_regvals_ibm()
494 MHz = yres == 960 ? 126 : 135; in compute_imstt_regvals_ibm()
[all …]
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| /drivers/gpu/drm/gma500/ |
| D | psb_device.c | 46 #define MHz 1000000 macro
87 value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT; in psb_backlight_setup()
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| D | oaktrail_device.c | 55 #define MHz 1000000 macro
123 value = (core_clock * MHz) / BLC_PWM_FREQ_CALC_CONSTANT; in device_backlight_init()
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| D | mdfld_device.c | 33 #define MHz 1000000 macro
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| /drivers/media/tuners/ |
| D | mxl5007t.c | 66 #define MHz 1000000 macro
436 dig_rf_freq = rf_freq / MHz; in mxl5007t_calc_rf_tune_regs()
438 temp = rf_freq % MHz; in mxl5007t_calc_rf_tune_regs()
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| /drivers/net/wireless/mwifiex/ |
| D | README | 44 iw dev mlan0 connect -w <SSID> [<freq in MHz>] [<bssid>] [key 0:abcde d:1123456789a]
54 iw dev mlan0 ibss join <SSID> <freq in MHz> [fixed-freq] [fixed-bssid] [key 0:abcde]
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| /drivers/video/omap2/dss/ |
| D | Kconfig | 105 Max FCK is 173MHz, so this doesn't work if your PCK
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| /drivers/gpu/drm/i915/ |
| D | intel_drv.h | 68 #define MHz(x) KHz(1000*x) macro
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| D | intel_display.c | 5474 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; in ironlake_fdi_set_m_n()
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| /drivers/scsi/aic7xxx/ |
| D | aic79xx.reg | 2747 * 960MHz Phase-Locked Loop Control 0
2774 * 960MHz Phase-Locked Loop Control 1
2815 * 960-MHz Phase-Locked Loop Test Count
2825 * 400-MHz Phase-Locked Loop Control 0
2851 * 400-MHz Phase-Locked Loop Control 1
2873 * 400-MHz Phase-Locked Loop Test Count
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| /drivers/mtd/devices/ |
| D | Kconfig | 99 bool "Use FAST_READ OPCode allowing SPI CLK >= 50MHz"
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| /drivers/leds/ |
| D | Kconfig | 72 The LM3642 is a 4MHz fixed-frequency synchronous boost
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| /drivers/regulator/ |
| D | Kconfig | 225 phase operates at a 2MHz fixed frequency with a 120 deg shift
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| /drivers/misc/ |
| D | Kconfig | 77 TC block with a 5+ MHz base clock rate. Two timer channels
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| /drivers/watchdog/ |
| D | Kconfig | 196 signal, so with reasonably fast systems (PCLK around 50-66MHz)
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| /drivers/eisa/ |
| D | eisa.ids | 398 CPQFD13 "Compaq 15MHz ESDI Fixed Disk Controller 001283"
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| /drivers/scsi/ |
| D | Kconfig | 1251 int "synchronous transfers frequency in MHz"
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