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Searched refs:MI_FLUSH (Results 1 – 6 of 6) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_ringbuffer.c62 cmd = MI_FLUSH; in gen2_render_ring_flush()
117 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; in gen4_render_ring_flush()
924 intel_ring_emit(ring, MI_FLUSH); in bsd_ring_flush()
1064 intel_ring_emit(ring, MI_FLUSH); in i830_dispatch_execbuffer()
Di915_dma.c529 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); in i915_dispatch_batchbuffer()
560 OUT_RING(MI_FLUSH | MI_READ_FLUSH); in i915_dispatch_flip()
Di915_reg.h200 #define MI_FLUSH MI_INSTR(0x04, 0) macro
Dintel_pm.c2841 intel_ring_emit(ring, MI_FLUSH); in ironlake_enable_rc6()
/drivers/video/intelfb/
Dintelfbhw.h474 #define MI_FLUSH (0x04 << 23) macro
Dintelfbhw.c1553 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE); in do_flush()