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Searched refs:PCH_DREF_CONTROL (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/i915/
Di915_ums.c111 dev_priv->regfile.savePCH_DREF_CONTROL = I915_READ(PCH_DREF_CONTROL); in i915_save_display_reg()
335 I915_WRITE(PCH_DREF_CONTROL, dev_priv->regfile.savePCH_DREF_CONTROL); in i915_restore_display_reg()
Dintel_display.c1320 val = I915_READ(PCH_DREF_CONTROL); in assert_pch_refclk_enabled()
4822 val = I915_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()
4880 I915_WRITE(PCH_DREF_CONTROL, val); in ironlake_init_pch_refclk()
4881 POSTING_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()
4897 I915_WRITE(PCH_DREF_CONTROL, val); in ironlake_init_pch_refclk()
4898 POSTING_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()
4908 I915_WRITE(PCH_DREF_CONTROL, val); in ironlake_init_pch_refclk()
4909 POSTING_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()
4919 I915_WRITE(PCH_DREF_CONTROL, val); in ironlake_init_pch_refclk()
4920 POSTING_READ(PCH_DREF_CONTROL); in ironlake_init_pch_refclk()
Di915_reg.h3749 #define PCH_DREF_CONTROL 0xC6200 macro