Searched refs:PCH_PP_CONTROL (Results 1 – 6 of 6) sorted by relevance
268 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; in ironlake_edp_have_panel_vdd()283 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; in intel_dp_check_edp()925 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; in ironlake_wait_panel_status()969 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; in ironlake_get_pp_control()1005 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; in ironlake_edp_panel_vdd_on()1034 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; in ironlake_panel_vdd_off_sync()1103 I915_WRITE(PCH_PP_CONTROL, pp); in ironlake_edp_panel_on()1104 POSTING_READ(PCH_PP_CONTROL); in ironlake_edp_panel_on()1111 pp_ctrl_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_CONTROL : PCH_PP_CONTROL; in ironlake_edp_panel_on()1120 I915_WRITE(PCH_PP_CONTROL, pp); in ironlake_edp_panel_on()[all …]
188 ctl_reg = PCH_PP_CONTROL; in intel_enable_lvds()213 ctl_reg = PCH_PP_CONTROL; in intel_disable_lvds()1264 I915_WRITE(PCH_PP_CONTROL, in intel_lvds_init()1265 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); in intel_lvds_init()
207 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL); in i915_save_display()294 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL); in i915_restore_display()
4135 #define PCH_PP_CONTROL 0xc7204 macro
1197 pp_reg = PCH_PP_CONTROL; in assert_panel_unlocked()
3167 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; in reset_ivb_igd()3168 iowrite32(val, mmio_base + PCH_PP_CONTROL); in reset_ivb_igd()