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Searched refs:PIPECONF (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_display.c974 int reg = PIPECONF(cpu_transcoder); in intel_wait_for_pipe_off()
1234 reg = PIPECONF(cpu_transcoder); in assert_pipe()
1711 pipeconf_val = I915_READ(PIPECONF(pipe)); in ironlake_enable_pch_transcoder()
1755 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); in lpt_enable_pch_transcoder()
1860 reg = PIPECONF(cpu_transcoder); in intel_enable_pipe()
1900 reg = PIPECONF(cpu_transcoder); in intel_disable_pipe()
2857 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_pll_enable()
2927 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
2956 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
3166 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; in ironlake_pch_enable()
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Dintel_crt.c487 pipeconf_reg = PIPECONF(pipe); in intel_crt_load_detect()
Dintel_sprite.c625 if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE)) in intel_update_plane()
Dintel_tv.c1089 int pipeconf_reg = PIPECONF(pipe); in intel_tv_mode_set()
Dintel_overlay.c831 … (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE) in check_overlay_possible_on_crtc()
Di915_reg.h2770 #define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF) macro
Di915_irq.c187 return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE; in i915_pipe_enabled()