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Searched refs:PIPECONF_BPC_MASK (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_display.c1718 val &= ~PIPECONF_BPC_MASK; in ironlake_enable_pch_transcoder()
1719 val |= pipeconf_val & PIPECONF_BPC_MASK; in ironlake_enable_pch_transcoder()
2857 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_pll_enable()
2927 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
2956 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; in ironlake_fdi_disable()
3166 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; in ironlake_pch_enable()
4581 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN); in i9xx_set_pipeconf()
5141 val &= ~PIPECONF_BPC_MASK; in ironlake_set_pipeconf()
Di915_reg.h2720 #define PIPECONF_BPC_MASK (0x7 << 5) macro