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Searched refs:PIPE_A (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/i915/
Di915_ums.c46 dpll_reg = (pipe == PIPE_A) ? _DPLL_A : _DPLL_B; in i915_pipe_enabled()
54 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B); in i915_save_palette()
62 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B; in i915_save_palette()
64 if (pipe == PIPE_A) in i915_save_palette()
76 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B); in i915_restore_palette()
84 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B; in i915_restore_palette()
86 if (pipe == PIPE_A) in i915_restore_palette()
169 i915_save_palette(dev, PIPE_A); in i915_save_display_reg()
404 i915_restore_palette(dev, PIPE_A); in i915_restore_display_reg()
Dintel_pm.c1304 if (g4x_compute_wm0(dev, PIPE_A, in valleyview_update_wm()
1308 enabled |= 1 << PIPE_A; in valleyview_update_wm()
1360 if (g4x_compute_wm0(dev, PIPE_A, in g4x_update_wm()
1364 enabled |= 1 << PIPE_A; in g4x_update_wm()
1719 if (g4x_compute_wm0(dev, PIPE_A, in ironlake_update_wm()
1730 enabled |= 1 << PIPE_A; in ironlake_update_wm()
1804 if (g4x_compute_wm0(dev, PIPE_A, in sandybridge_update_wm()
1815 enabled |= 1 << PIPE_A; in sandybridge_update_wm()
1907 if (g4x_compute_wm0(dev, PIPE_A, in ivybridge_update_wm()
1918 enabled |= 1 << PIPE_A; in ivybridge_update_wm()
Dintel_ddi.c994 case PIPE_A: in intel_ddi_enable_transcoder_func()
1128 *pipe = PIPE_A; in intel_ddi_get_hw_state()
Dintel_display.c1193 enum pipe panel_pipe = PIPE_A; in assert_panel_unlocked()
1227 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) in assert_pipe()
1515 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) in intel_disable_pll()
1897 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) in intel_disable_pipe()
5371 case PIPE_A: in ironlake_check_fdi_lanes()
5759 if (crtc->pipe != PIPE_A && crtc->base.enabled) in haswell_modeset_global_resources()
5883 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE) in haswell_get_pipe_config()
7942 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) in intel_modeset_check_state()
9199 crtc->pipe == PIPE_A && !crtc->active) { in intel_sanitize_crtc()
9312 pipe = PIPE_A; in intel_modeset_setup_hw_state()
Di915_drv.h57 PIPE_A = 0, enumerator
/drivers/video/intelfb/
Dintelfbhw.c480 if (unlikely(pipe == PIPE_A)) in intelfbhw_active_pipe()
481 return PIPE_A; in intelfbhw_active_pipe()
486 if (likely(pipe == PIPE_A)) in intelfbhw_active_pipe()
487 return PIPE_A; in intelfbhw_active_pipe()
492 pipe = PIPE_A; in intelfbhw_active_pipe()
501 u32 palette_reg = (dinfo->pipe == PIPE_A) ? in intelfbhw_setcolreg()
Dintelfbhw.h182 #define PIPE_A 0 macro