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Searched refs:PIPE_B (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_pm.c1310 if (g4x_compute_wm0(dev, PIPE_B, in valleyview_update_wm()
1314 enabled |= 1 << PIPE_B; in valleyview_update_wm()
1366 if (g4x_compute_wm0(dev, PIPE_B, in g4x_update_wm()
1370 enabled |= 1 << PIPE_B; in g4x_update_wm()
1733 if (g4x_compute_wm0(dev, PIPE_B, in ironlake_update_wm()
1744 enabled |= 1 << PIPE_B; in ironlake_update_wm()
1818 if (g4x_compute_wm0(dev, PIPE_B, in sandybridge_update_wm()
1829 enabled |= 1 << PIPE_B; in sandybridge_update_wm()
1921 if (g4x_compute_wm0(dev, PIPE_B, in ivybridge_update_wm()
1932 enabled |= 1 << PIPE_B; in ivybridge_update_wm()
Di915_ums.c226 i915_save_palette(dev, PIPE_B); in i915_save_display_reg()
473 i915_restore_palette(dev, PIPE_B); in i915_restore_display_reg()
Dintel_ddi.c1003 case PIPE_B: in intel_ddi_enable_transcoder_func()
1131 *pipe = PIPE_B; in intel_ddi_get_hw_state()
Dintel_display.c1210 panel_pipe = PIPE_B; in assert_panel_unlocked()
2474 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); in ivb_modeset_global_resources()
2483 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); in ivb_modeset_global_resources()
3739 pipe = PIPE_B; in i9xx_pfit_disable()
4548 (pipe == PIPE_B || pipe == PIPE_C)) in intel_set_pipe_timings()
5340 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); in cpt_enable_fdi_bc_bifurcation()
5354 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); in ironlake_check_fdi_lanes()
5373 case PIPE_B: in ironlake_check_fdi_lanes()
9315 pipe = PIPE_B; in intel_modeset_setup_hw_state()
Di915_drv.h58 PIPE_B, enumerator
/drivers/video/intelfb/
Dintelfbhw.h183 #define PIPE_B 1 macro
Dintelfbhw.c1062 if (pipe == PIPE_B) { in intelfbhw_mode_to_hw()
1306 if (dinfo->pipe == PIPE_B) { in intelfbhw_program_mode()