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Searched refs:PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (Results 1 – 2 of 2) sorted by relevance

/drivers/gpu/drm/i915/
Dintel_ringbuffer.c240 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; in gen6_render_ring_flush()
312 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; in gen7_render_ring_flush()
Di915_reg.h324 #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */ macro