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Searched refs:PORT_REG (Results 1 – 3 of 3) sorted by relevance

/drivers/scsi/csiostor/
Dcsio_hw_chip.h127 (csio_is_t4(hw->chip_id) ? (PORT_REG(port, XGMAC_PORT_INT_CAUSE)) : \
/drivers/net/ethernet/chelsio/cxgb4/
Dt4_hw.c1777 int_cause_reg = PORT_REG(port, XGMAC_PORT_INT_CAUSE); in xgmac_intr_handler()
1793 t4_write_reg(adap, PORT_REG(port, XGMAC_PORT_INT_CAUSE), v); in xgmac_intr_handler()
2244 (is_t4(adap->chip) ? PORT_REG(idx, MPS_PORT_STAT_##name##_L) : \ in t4_get_port_stats()
2327 mag_id_reg_l = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_LO); in t4_wol_magic_enable()
2328 mag_id_reg_h = PORT_REG(port, XGMAC_PORT_MAGIC_MACID_HI); in t4_wol_magic_enable()
2329 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2); in t4_wol_magic_enable()
2369 port_cfg_reg = PORT_REG(port, XGMAC_PORT_CFG2); in t4_wol_pat_enable()
2381 (is_t4(adap->chip) ? PORT_REG(port, XGMAC_PORT_EPIO_##name) : \ in t4_wol_pat_enable()
2408 t4_set_reg_field(adap, PORT_REG(port, XGMAC_PORT_CFG2), 0, PATEN); in t4_wol_pat_enable()
Dt4_regs.h56 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg)) macro