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Searched refs:R9 (Results 1 – 14 of 14) sorted by relevance

/drivers/media/i2c/
Dwm8739.c50 R5 = 5, R6, R7, R8, R9, R15 = 15, enumerator
141 wm8739_write(sd, R9, 0x000); in wm8739_s_clock_freq()
159 wm8739_write(sd, R9, 0x001); in wm8739_s_clock_freq()
261 wm8739_write(sd, R9, 0x001); in wm8739_probe()
/drivers/tty/serial/
Dsunzilog.c1337 write_zsreg(channel, R9, FHWRES); in sunzilog_init_hw()
1350 up->curregs[R9] = NV; in sunzilog_init_hw()
1355 up->curregs[R9] |= MIE; in sunzilog_init_hw()
1356 write_zsreg(channel, R9, up->curregs[R9]); in sunzilog_init_hw()
1366 up->curregs[R9] = NV; in sunzilog_init_hw()
1381 up->curregs[R9] |= MIE; in sunzilog_init_hw()
1382 write_zsreg(channel, R9, up->curregs[R9]); in sunzilog_init_hw()
1591 up->curregs[R9] |= MIE; in sunzilog_init()
1592 write_zsreg(channel, R9, up->curregs[R9]); in sunzilog_init()
1628 up->curregs[R9] &= ~MIE; in sunzilog_exit()
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Dzs.h68 #define R9 9 macro
Dip22zilog.h47 #define R9 9 macro
Dsunzilog.h39 #define R9 9 macro
Dip22zilog.c699 write_zsreg(channel, R9, FHWRES); in __ip22zilog_reset()
717 write_zsreg(channel, R9, up->curregs[R9]); in __ip22zilog_startup()
1136 up->curregs[R9] = NV | MIE; in ip22zilog_prepare()
Dpmac_zilog.h135 #define R9 9 macro
Dpmac_zilog.c195 write_zsreg(uap, R9, regs[R9]); in pmz_load_zsregs()
855 uap->curregs[R9] = 0; in __pmz_startup()
883 uap->curregs[R9] |= NV | MIE; in __pmz_startup()
Dzs.c275 write_zsreg(zport, R9, regs[9]); in load_zsregs()
842 write_zsreg(zport, R9, FHWRES); in zs_reset()
844 write_zsreg(zport, R9, 0); in zs_reset()
/drivers/net/hamradio/
Dz8530.h15 #define R9 9 macro
Ddmascc.c295 write_scc(&info->priv[0], R9, FHWRES); in dmascc_exit()
494 write_scc(priv, R9, FHWRES | MIE | NV); in setup_adapter()
608 write_scc(&info->priv[0], R9, FHWRES); in setup_adapter()
755 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_open()
877 write_scc(priv, R9, (priv->channel ? CHRB : CHRA) | MIE | NV); in scc_close()
Dscc.c805 wr(scc,R9,VIS); /* vector includes status */ in init_channel()
880 or(scc,R9,MIE); /* master interrupt enable */ in init_channel()
1498 OutReg(scc->ctrl,R9,FHWRES); /* force hardware reset */ in z8530_init()
1501 wr(scc, R9, VIS); /* vector includes status */ in z8530_init()
1760 OutReg(hwcfg.ctrl_a, R9, FHWRES); in scc_net_ioctl()
2146 OutReg(ctrl,R9,FHWRES); /* force hardware reset */ in scc_cleanup_driver()
/drivers/net/wan/
Dz85230.h34 #define R9 9 macro
Dz85230.c1255 write_zsreg(&dev->chanA, R9, 0xC0); in do_z8530_init()
1363 write_zsreg(&dev->chanA, R9, 0xC0); in z8530_shutdown()