/drivers/video/omap2/dss/ |
D | ti_hdmi_4xxx_ip.c | 98 REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0); in hdmi_pll_init() 115 REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10); in hdmi_pll_init() 130 REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0); in hdmi_pll_init() 165 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6); in hdmi_set_phy_pwr() 181 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2); in hdmi_set_pll_pwr() 196 REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3); in hdmi_pll_reset() 289 REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30); in ti_hdmi_4xxx_phy_enable() 295 REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); in ti_hdmi_4xxx_phy_enable() 298 REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27); in ti_hdmi_4xxx_phy_enable() 332 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0); in hdmi_core_ddc_init() [all …]
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D | dss.c | 61 #define REG_FLD_MOD(idx, val, start, end) \ macro 199 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_enable() 203 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */ in dss_sdi_enable() 215 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28); in dss_sdi_enable() 243 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_enable() 257 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */ in dss_sdi_disable() 350 REG_FLD_MOD(DSS_CONTROL, b, start, end); /* DISPC_CLK_SWITCH */ in dss_select_dispc_clk_source() 383 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* DSIx_CLK_SWITCH */ in dss_select_dsi_clk_source() 423 REG_FLD_MOD(DSS_CONTROL, b, pos, pos); /* LCDx_CLK_SWITCH */ in dss_select_lcd_clk_source() 601 REG_FLD_MOD(DSS_CONTROL, l, 6, 6); in dss_set_venc_output() [all …]
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D | dispc.c | 58 #define REG_FLD_MOD(idx, val, start, end) \ macro 247 REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low); in mgr_fld_write() 580 REG_FLD_MOD(DISPC_CONTROL2, 1, 6, 6); in dispc_wb_go() 677 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_ovl_write_color_conv_coef() 766 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); in dispc_ovl_set_zorder() 777 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); in dispc_ovl_enable_zorder_planes() 786 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); in dispc_ovl_set_pre_mult_alpha() 799 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); in dispc_ovl_setup_global_alpha() 890 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); in dispc_ovl_set_color_mode() 900 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); in dispc_ovl_configure_burst_type() [all …]
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D | dsi.c | 111 #define REG_FLD_MOD(dsidev, idx, val, start, end) \ macro 1175 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */ in dsi_if_enable() 1262 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0); in dsi_set_lp_clk_divisor() 1265 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21); in dsi_set_lp_clk_divisor() 1275 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */ in dsi_enable_scp_clk() 1284 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */ in dsi_disable_scp_clk() 1305 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30); in dsi_pll_power() 1501 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0); in dsi_pll_set_clock_div() 1542 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */ in dsi_pll_set_clock_div() 1971 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27); in dsi_cio_power() [all …]
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D | rfbi.c | 69 #define REG_FLD_MOD(idx, val, start, end) \ macro 351 REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0); in framedone_callback() 463 REG_FLD_MOD(RFBI_CONFIG(rfbi_module), in rfbi_set_timings() 737 REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */ in rfbi_configure()
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D | ti_hdmi_4xxx_ip.h | 177 #define REG_FLD_MOD(base, idx, val, start, end) \ macro
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/drivers/gpu/drm/gma500/ |
D | mdfld_dsi_dpi.c | 113 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), !!state, 0, 0); in dsi_set_device_ready_state() 146 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 2, 2, 1); in dsi_set_pipe_plane_enable_state() 150 REG_FLD_MOD(MIPI_PORT_CONTROL(pipe), 0, 16, 16); in dsi_set_pipe_plane_enable_state() 154 REG_FLD_MOD(dspcntr_reg, 0, 31, 31); in dsi_set_pipe_plane_enable_state() 161 REG_FLD_MOD(pipeconf_reg, 0, 31, 31); in dsi_set_pipe_plane_enable_state() 476 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 0, 0, 0); in mdfld_dsi_dpi_controller_init() 565 REG_FLD_MOD(MIPI_DEVICE_READY_REG(pipe), 1, 0, 0); in mdfld_dsi_dpi_controller_init()
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D | mdfld_dsi_output.h | 50 #define REG_FLD_MOD(reg, val, start, end) \ macro
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