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Searched refs:REG_GET (Results 1 – 6 of 6) sorted by relevance

/drivers/video/omap2/dss/
Dti_hdmi_4xxx_ip.c83 while (val != REG_GET(base_addr, idx, b2, b1)) { in hdmi_wait_for_bit_change()
161 if (REG_GET(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, 5, 4) == val) in hdmi_set_phy_pwr()
335 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) { in hdmi_core_ddc_init()
407 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) { in hdmi_core_ddc_edid()
412 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) { in hdmi_core_ddc_edid()
421 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) { in hdmi_core_ddc_edid()
428 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) { in hdmi_core_ddc_edid()
436 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0); in hdmi_core_ddc_edid()
Ddsi.c108 #define REG_GET(dsidev, idx, start, end) \ macro
466 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) in wait_for_bit_change()
473 if (REG_GET(dsidev, idx, bitnum, bitnum) == value) in wait_for_bit_change()
1998 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */ in dsi_get_line_buf_size()
2494 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0); in dsi_vc_is_enabled()
2505 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0) in dsi_packet_sent_handler_vp()
2525 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) { in dsi_sync_vc_vp()
2552 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0) in dsi_packet_sent_handler_l4()
2568 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) { in dsi_sync_vc_l4()
2724 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) { in dsi_vc_flush_long_data()
[all …]
Ddispc.c55 #define REG_GET(idx, start, end) \ macro
241 return REG_GET(rfld.reg, rfld.high, rfld.low); in mgr_fld_read()
561 return REG_GET(DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go_busy()
569 enable = REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; in dispc_wb_go()
574 go = REG_GET(DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go()
1127 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(fifo), start, end); in dispc_init_fifos()
1193 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1195 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
2633 return REG_GET(DISPC_OVL_ATTRIBUTES(plane), 0, 0); in dispc_ovl_enabled()
3432 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_get_clock_div()
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Ddss.c58 #define REG_GET(idx, start, end) \ macro
634 return REG_GET(DSS_CONTROL, 15, 15); in dss_get_hdmi_venc_clk_source()
Dti_hdmi_4xxx_ip.h180 #define REG_GET(base, idx, start, end) \ macro
/drivers/gpu/drm/radeon/
Dradeon.h1748 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) macro