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Searched refs:REG_SET_BIT (Results 1 – 16 of 16) sorted by relevance

/drivers/net/wireless/ath/ath9k/
Dwow.c52 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV); in ath9k_hw_set_powermode_wow_sleep()
147 REG_SET_BIT(ah, AR_WOW_PATTERN, BIT(pattern_count)); in ath9k_hw_wow_apply_pattern()
263 REG_SET_BIT(ah, AR_WA, AR_WA_UNTIE_RESET_EN | in ath9k_hw_wow_wakeup()
365 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set); in ath9k_hw_wow_enable()
383 REG_SET_BIT(ah, AR_WOW_PATTERN, set); in ath9k_hw_wow_enable()
388 REG_SET_BIT(ah, AR_WOW_COUNT, set); in ath9k_hw_wow_enable()
513 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, set); in ath9k_hw_wow_enable()
523 REG_SET_BIT(ah, AR_PCIE_PHY_REG3, set); in ath9k_hw_wow_enable()
Dmac.c148 REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF); in ath9k_hw_abort_tx_dma()
149 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH); in ath9k_hw_abort_tx_dma()
150 REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF); in ath9k_hw_abort_tx_dma()
424 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR | in ath9k_hw_resettxqueue()
440 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY); in ath9k_hw_resettxqueue()
443 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS); in ath9k_hw_resettxqueue()
448 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN); in ath9k_hw_resettxqueue()
454 REG_SET_BIT(ah, AR_QMISC(q), in ath9k_hw_resettxqueue()
459 REG_SET_BIT(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
482 REG_SET_BIT(ah, AR_QMISC(q), in ath9k_hw_resettxqueue()
[all …]
Dar9002_calib.c77 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_setup_calibration()
259 REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0), in ar9002_hw_iqcalibrate()
723 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); in ar9285_hw_cl_cal()
725 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); in ar9285_hw_cl_cal()
726 REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); in ar9285_hw_cl_cal()
730 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
743 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); in ar9285_hw_cl_cal()
744 REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); in ar9285_hw_cl_cal()
745 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); in ar9285_hw_cl_cal()
754 REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); in ar9285_hw_cl_cal()
[all …]
Dar9002_phy.c433 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9, in ar9002_olc_init()
568 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); in ar9002_hw_spectral_scan_config()
569 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9002_hw_spectral_scan_config()
572 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_config()
600 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9002_hw_spectral_scan_trigger()
602 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, in ar9002_hw_spectral_scan_trigger()
Dar9003_phy.c596 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar9003_hw_set_chain_masks()
620 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar9003_hw_override_ini()
633 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, in ar9003_hw_override_ini()
923 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar9003_hw_ani_control()
1247 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar9003_hw_set_radar_params()
1352 REG_SET_BIT(ah, AR_PHY_MC_GAIN_CTRL, in ar9003_hw_antctrl_shared_chain_lnadiv()
1355 REG_SET_BIT(ah, AR_PHY_RESTART, in ar9003_hw_antctrl_shared_chain_lnadiv()
1357 REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, in ar9003_hw_antctrl_shared_chain_lnadiv()
1455 REG_SET_BIT(ah, AR_PHY_RADAR_0, AR_PHY_RADAR_0_FFT_ENA); in ar9003_hw_spectral_scan_config()
1456 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENABLE); in ar9003_hw_spectral_scan_config()
[all …]
Dar9002_hw.c337 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9002_hw_configpcipowersave()
391 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
393 REG_SET_BIT(ah, AR_PHY_MODE, AR_PHY_MODE_ASYNCFIFO); in ar9002_hw_enable_async_fifo()
396 REG_SET_BIT(ah, AR_MAC_PCU_ASYNC_FIFO_REG3, in ar9002_hw_enable_async_fifo()
Dhw.c774 REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK); in ar9003_get_pll_sqsum_dvc()
866 REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16); in ath9k_hw_init_pll()
1054 REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode); in ath9k_hw_init_global_settings()
1183 REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN); in ath9k_hw_set_dma()
1255 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION); in ath9k_hw_set_operating_mode()
1696 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_init_mfp()
1939 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); in ath9k_hw_reset()
1989 REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER, in ath9k_hw_reset()
1993 REG_SET_BIT(ah, AR_PCU_MISC_MODE2, in ath9k_hw_reset()
1997 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM); in ath9k_hw_reset()
[all …]
Dar9003_mci.c447 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE); in ar9003_mci_observation_set_up()
451 REG_SET_BIT(ah, AR_GLB_GPIO_CONTROL, ATH_MCI_CONFIG_MCI_OBS_GPIO); in ar9003_mci_observation_set_up()
764 REG_SET_BIT(ah, AR_PHY_TIMING4, in ar9003_mci_end_reset()
776 REG_SET_BIT(ah, AR_MCI_TX_CTRL, AR_MCI_TX_CTRL_DISABLE_LNA_UPDATE); in ar9003_mci_mute_bt()
878 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, in ar9003_mci_reset()
903 REG_SET_BIT(ah, AR_BTCOEX_CTRL, AR_BTCOEX_CTRL_MCI_MODE_EN); in ar9003_mci_reset()
1071 REG_SET_BIT(ah, AR_MCI_TX_CTRL, in ar9003_mci_2g5g_switch()
1073 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, in ar9003_mci_2g5g_switch()
1305 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_BT_OWN_SPDT_CTRL); in ar9003_mci_bt_gain_ctrl()
1342 REG_SET_BIT(ah, AR_BTCOEX_RC, 0x1); in ar9003_mci_set_power_awake()
Dcalib.c225 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
232 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_start_nfcal()
235 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ath9k_hw_start_nfcal()
278 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF); in ath9k_hw_loadnf()
Dar5008_phy.c567 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
592 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, in ar5008_hw_init_chain_masks()
610 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT)); in ar5008_hw_override_ini()
624 REG_SET_BIT(ah, AR_PHY_CCK_DETECT, in ar5008_hw_override_ini()
758 REG_SET_BIT(ah, AR_PHY_SPECTRAL_SCAN, AR_PHY_SPECTRAL_SCAN_ENA); in ar5008_hw_process_ini()
998 REG_SET_BIT(ah, AR_PHY_SFCORR_LOW, in ar5008_hw_ani_control_new()
1294 REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); in ar5008_hw_set_radar_params()
Dbtcoex.c140 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, in ath9k_hw_btcoex_init_2wire()
158 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, in ath9k_hw_btcoex_init_3wire()
Dar9003_calib.c58 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); in ar9003_hw_setup_calibration()
299 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0, in ar9003_hw_iqcalibrate()
1059 REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, in ar9003_hw_init_cal()
1080 REG_SET_BIT(ah, AR_PHY_TX_IQCAL_CONTROL_0, in ar9003_hw_init_cal()
Dar9003_hw.c673 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA); in ar9003_hw_configpcipowersave()
Dhw.h111 #define REG_SET_BIT(_a, _r, _f) \ macro
Dar9003_paprd.c939 REG_SET_BIT(ah, AR_PHY_CHAN_INFO_MEMORY, in ar9003_paprd_create_curve()
Dar9003_eeprom.c3603 REG_SET_BIT(ah, AR_PHY_GLB_CONTROL, AR_BTCOEX_CTRL_SPDT_ENABLE); in ar9003_hw_ant_ctrl_apply()