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Searched refs:SET (Results 1 – 13 of 13) sorted by relevance

/drivers/clk/mxs/
Dclk-pll.c43 writel_relaxed(1 << pll->power, pll->base + SET); in clk_pll_prepare()
70 writel_relaxed(1 << 31, pll->base + SET); in clk_pll_disable()
Dclk-imx28.c79 writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET); in mxs_saif_clkmux_select()
89 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); in clk_misc_init()
92 writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET); in clk_misc_init()
Dclk-imx23.c54 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET); in clk_misc_init()
75 writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET); in clk_misc_init()
Dclk.h19 #define SET 0x4 macro
Dclk-ref.c51 writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + SET); in clk_ref_disable()
/drivers/pwm/
Dpwm-mxs.c25 #define SET 0x4 macro
107 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + SET); in mxs_pwm_enable()
/drivers/pinctrl/
Dpinctrl-mxs.c216 writel(g->muxsel[i] << shift, reg + SET); in mxs_pinctrl_enable()
277 writel(ma << shift, reg + SET); in mxs_pinconf_group_set()
284 writel(1 << shift, reg + SET); in mxs_pinconf_group_set()
295 writel(1 << shift, reg + SET); in mxs_pinconf_group_set()
Dpinctrl-mxs.h18 #define SET 0x4 macro
/drivers/mtd/nand/
Ddenali.h368 #define SET 1 /*use this to set a field instead of "pass"*/ macro
/drivers/scsi/
D53c700.scr164 SET TARGET
239 SET ATN
D53c700_d.h_shipped200 SET TARGET
395 SET ATN
/drivers/gpu/drm/nouveau/core/engine/graph/
Dctxnv50.c196 cp_set (ctx, UNK01, SET); in nv50_grctx_generate()
202 cp_bra (ctx, UNK0B, SET, cp_prepare_exit); in nv50_grctx_generate()
207 cp_set (ctx, UNK1D, SET); in nv50_grctx_generate()
211 cp_set (ctx, UNK01, SET); in nv50_grctx_generate()
216 cp_set (ctx, UNK03, SET); in nv50_grctx_generate()
226 cp_set (ctx, UNK20, SET); in nv50_grctx_generate()
/drivers/net/fddi/skfp/h/
Dskfbi.h1042 #define SET(io,mask) outpw((io),inpw(io)|(mask)) macro