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Searched refs:SET_FIELD (Results 1 – 4 of 4) sorted by relevance

/drivers/net/wireless/rt2x00/
Drt2x00reg.h248 #define SET_FIELD(__reg, __type, __field, __value)\ macro
265 SET_FIELD(__reg, struct rt2x00_field32, __field, __value)
270 SET_FIELD(__reg, struct rt2x00_field16, __field, __value)
275 SET_FIELD(__reg, struct rt2x00_field8, __field, __value)
/drivers/staging/crystalhd/
Dbcm_70012_regs.h27 #if !defined(GET_FIELD) && !defined(SET_FIELD)
36 #define SET_FIELD(m, c, r, f, d) \ macro
41 #define SET_TYPE_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, c##_##d)
42 #define SET_NAME_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, c##_##r##_##f##_##d)
43 #define SET_VALUE_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, d)
/drivers/gpu/drm/gma500/
Dcdv_intel_display.c186 SET_FIELD(SB_OPCODE_READ, SB_OPCODE) | in cdv_sb_read()
187 SET_FIELD(SB_DEST_DPLL, SB_DEST) | in cdv_sb_read()
188 SET_FIELD(0xf, SB_BYTE_ENABLE)); in cdv_sb_read()
222 SET_FIELD(SB_OPCODE_WRITE, SB_OPCODE) | in cdv_sb_write()
223 SET_FIELD(SB_DEST_DPLL, SB_DEST) | in cdv_sb_write()
224 SET_FIELD(0xf, SB_BYTE_ENABLE)); in cdv_sb_write()
356 p |= SET_FIELD(clock->p1, SB_P1_DIVIDER); in cdv_dpll_set_clock_cdv()
359 p |= SET_FIELD(SB_P2_5, SB_P2_DIVIDER); in cdv_dpll_set_clock_cdv()
362 p |= SET_FIELD(SB_P2_10, SB_P2_DIVIDER); in cdv_dpll_set_clock_cdv()
365 p |= SET_FIELD(SB_P2_14, SB_P2_DIVIDER); in cdv_dpll_set_clock_cdv()
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Dpsb_intel_reg.h1292 #define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK) macro