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Searched refs:TEGRA_DIVIDER_2 (Results 1 – 3 of 3) sorted by relevance

/drivers/clk/tegra/
Dclk-super.c65 if ((mux->flags & TEGRA_DIVIDER_2) && !(val & SUPER_LP_DIV2_BYPASS) && in clk_super_get_parent()
96 if ((mux->flags & TEGRA_DIVIDER_2) && ((index == mux->div2_index) || in clk_super_set_parent()
Dclk.h527 #define TEGRA_DIVIDER_2 BIT(0) macro
Dclk-tegra30.c1342 TEGRA_DIVIDER_2, 4, 8, 9, in tegra30_super_clk_init()