| /drivers/net/ethernet/qlogic/qlcnic/ |
| D | qlcnic_hdr.h | 642 #define QLC_DEV_SET_REF_CNT(VAL, FN) ((VAL) |= (1 << (FN * 4))) argument
643 #define QLC_DEV_CLR_REF_CNT(VAL, FN) ((VAL) &= ~(1 << (FN * 4))) argument
644 #define QLC_DEV_SET_RST_RDY(VAL, FN) ((VAL) |= (1 << (FN * 4))) argument
645 #define QLC_DEV_SET_QSCNT_RDY(VAL, FN) ((VAL) |= (2 << (FN * 4))) argument
646 #define QLC_DEV_CLR_RST_QSCNT(VAL, FN) ((VAL) &= ~(3 << (FN * 4))) argument
648 #define QLC_DEV_GET_DRV(VAL, FN) (0xf & ((VAL) >> (FN * 4))) argument
649 #define QLC_DEV_SET_DRV(VAL, FN) ((VAL) << (FN * 4)) argument
678 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) argument
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| D | qlcnic_83xx_hw.h | 386 #define QLC_83XX_GET_FUNC_PRIVILEGE(VAL, FN) (0x3 & ((VAL) >> (FN * 2))) argument
387 #define QLC_83XX_SET_FUNC_OPMODE(VAL, FN) ((VAL) << (FN * 2)) argument
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| D | qlcnic.h | 777 #define QLCNIC_IS_LB_CONFIGURED(VAL) \ argument
778 (VAL == (QLCNIC_LINKEVENT | QLCNIC_LB_RESPONSE))
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| /drivers/net/ethernet/qlogic/netxen/ |
| D | netxen_nic_hdr.h | 964 #define NETXEN_DIMM_MEMTYPE(VAL) ((VAL >> 3) & 0xf) argument
965 #define NETXEN_DIMM_NUMROWS(VAL) ((VAL >> 7) & 0xf) argument
966 #define NETXEN_DIMM_NUMCOLS(VAL) ((VAL >> 11) & 0xf) argument
967 #define NETXEN_DIMM_NUMRANKS(VAL) ((VAL >> 15) & 0x3) argument
968 #define NETXEN_DIMM_DATAWIDTH(VAL) ((VAL >> 18) & 0x3) argument
969 #define NETXEN_DIMM_NUMBANKS(VAL) ((VAL >> 21) & 0xf) argument
970 #define NETXEN_DIMM_TYPE(VAL) ((VAL >> 25) & 0x3f) argument
1005 #define ISR_LEGACY_INT_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) argument
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| /drivers/watchdog/ |
| D | it8712f_wdt.c | 63 #define VAL 0x2f /* The value to read/write */ macro
101 return inb(VAL); in superio_inb()
107 outb(val, VAL); in superio_outb()
114 val = inb(VAL) << 8; in superio_inw()
116 val |= inb(VAL); in superio_inw()
123 outb(ldn, VAL); in superio_select()
144 outb(0x02, VAL); in superio_exit()
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| D | it87_wdt.c | 64 #define VAL 0x2f macro
185 outb(0x02, VAL); in superio_exit()
192 outb(ldn, VAL); in superio_select()
198 return inb(VAL); in superio_inb()
204 outb(val, VAL); in superio_outb()
211 val = inb(VAL) << 8; in superio_inw()
213 val |= inb(VAL); in superio_inw()
220 outb(val >> 8, VAL); in superio_outw()
222 outb(val, VAL); in superio_outw()
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| /drivers/staging/comedi/drivers/ |
| D | s626.h | 434 #define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24)) argument
435 #define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16)) argument
436 #define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8)) argument
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| D | s626.c | 178 #define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24)) argument
179 #define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16)) argument
180 #define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8)) argument
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| /drivers/rtc/ |
| D | rtc-at32ap700x.c | 75 now = rtc_readl(rtc, VAL); in at32_rtc_readtime()
89 rtc_writel(rtc, VAL, now); in at32_rtc_settime()
114 rtc_unix_time = rtc_readl(rtc, VAL); in at32_rtc_setalarm()
145 if (rtc_readl(rtc, VAL) > rtc->alarm_time) { in at32_rtc_alarm_irq_enable()
179 rtc_writel(rtc, VAL, rtc->alarm_time); in at32_rtc_interrupt()
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| /drivers/scsi/ |
| D | sun3x_esp.c | 44 #define dma_write32(VAL, REG) \
45 writel((VAL), esp->dma_regs + (REG))
49 #define dma_write32(VAL, REG) \ argument
50 do { *(volatile u32 *)(esp->dma_regs + (REG)) = (VAL); } while (0)
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| D | aha152x.h | 288 #define SETPORT(PORT, VAL) outb( (VAL), (PORT) ) argument
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| D | mac_esp.c | 49 #define esp_write8(VAL, REG) mac_esp_write8(esp, VAL, REG) argument
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| D | sun_esp.c | 32 #define dma_write32(VAL, REG) \ argument
33 sbus_writel((VAL), esp->dma_regs + (REG))
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| D | esp_scsi.c | 104 #define esp_write8(VAL,REG) esp->ops->esp_write8(esp, VAL, REG) argument
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| /drivers/hwmon/ |
| D | smsc47b397.c | 55 #define VAL 0x2f /* The value to read/write */ macro
60 outb(val, VAL); in superio_outb()
66 return inb(VAL); in superio_inb()
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| D | smsc47m1.c | 57 #define VAL 0x2f /* The value to read/write */ macro
63 outb(val, VAL); in superio_outb()
70 return inb(VAL); in superio_inb()
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| D | it87.c | 77 #define VAL 0x2f /* The value to read/write */ macro
89 return inb(VAL); in superio_inb()
95 outb(val, VAL); in superio_outb()
102 val = inb(VAL) << 8; in superio_inw()
104 val |= inb(VAL); in superio_inw()
111 outb(ldn, VAL); in superio_select()
132 outb(0x02, VAL); in superio_exit()
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| /drivers/net/ethernet/freescale/fs_enet/ |
| D | mii-fec.c | 47 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) argument
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| D | mac-fcc.c | 73 #define mk_mii_write(REG, VAL) (0x50020000 | ((REG & 0x1f) << 18) | (VAL & 0xffff)) argument
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| /drivers/scsi/qla4xxx/ |
| D | ql4_nx.h | 764 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0) argument
765 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) argument
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| /drivers/scsi/qla2xxx/ |
| D | qla_nx.h | 705 #define ISR_IS_LEGACY_INTR_IDLE(VAL) (((VAL) & 0x300) == 0) argument
706 #define ISR_IS_LEGACY_INTR_TRIGGERED(VAL) (((VAL) & 0x300) == 0x200) argument
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