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Searched refs:VIA_WRITE (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/via/
Dvia_irq.c152 VIA_WRITE(VIA_REG_INTERRUPT, status); in via_driver_irq_handler()
168 VIA_WRITE(VIA_REG_INTERRUPT, status | in viadrv_acknowledge_irqs()
184 VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_VBLANK_ENABLE); in via_enable_vblank()
198 VIA_WRITE(VIA_REG_INTERRUPT, status & ~VIA_IRQ_VBLANK_ENABLE); in via_disable_vblank()
302 VIA_WRITE(VIA_REG_INTERRUPT, status & in via_driver_irq_preinstall()
320 VIA_WRITE(VIA_REG_INTERRUPT, status | VIA_IRQ_GLOBAL in via_driver_irq_postinstall()
344 VIA_WRITE(VIA_REG_INTERRUPT, status & in via_driver_irq_uninstall()
Dvia_dma.c457 VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); in via_hook_segment()
458 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi); in via_hook_segment()
459 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo); in via_hook_segment()
539 VIA_WRITE(VIA_REG_TRANSET, (HC_ParaType_PreCR << 16)); in via_cmdbuf_start()
540 VIA_WRITE(VIA_REG_TRANSPACE, command); in via_cmdbuf_start()
541 VIA_WRITE(VIA_REG_TRANSPACE, start_addr_lo); in via_cmdbuf_start()
542 VIA_WRITE(VIA_REG_TRANSPACE, end_addr_lo); in via_cmdbuf_start()
544 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi); in via_cmdbuf_start()
545 VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo); in via_cmdbuf_start()
547 VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK); in via_cmdbuf_start()
Dvia_dmablit.c213 VIA_WRITE(VIA_PCI_DMA_MAR0 + engine*0x10, 0); in via_fire_dmablit()
214 VIA_WRITE(VIA_PCI_DMA_DAR0 + engine*0x10, 0); in via_fire_dmablit()
215 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DD | VIA_DMA_CSR_TD | in via_fire_dmablit()
217 VIA_WRITE(VIA_PCI_DMA_MR0 + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE); in via_fire_dmablit()
218 VIA_WRITE(VIA_PCI_DMA_BCR0 + engine*0x10, 0); in via_fire_dmablit()
219 VIA_WRITE(VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start); in via_fire_dmablit()
221 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS); in via_fire_dmablit()
294 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TA); in via_abort_dmablit()
302 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD | VIA_DMA_CSR_DD); in via_dmablit_engine_off()
352 VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_TD); in via_dmablit_handler()
Dvia_verifier.c726 VIA_WRITE(HC_REG_TRANS_SET + HC_REG_BASE, *buf++); in via_parse_header2()
733 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE + in via_parse_header2()
754 VIA_WRITE(HC_REG_TRANS_SPACE + HC_REG_BASE + in via_parse_header2()
844 VIA_WRITE((cmd & ~HALCYON_HEADER1MASK) << 2, *++buf); in via_parse_header1()
895 VIA_WRITE(addr, *buf++); in via_parse_vheader5()
951 VIA_WRITE(addr, *buf++); in via_parse_vheader6()
Dvia_drv.h113 #define VIA_WRITE(reg, val) DRM_WRITE32(VIA_BASE, reg, val) macro