Searched refs:VLV_DISPLAY_BASE (Results 1 – 4 of 4) sorted by relevance
355 #define DPIO_PKT (VLV_DISPLAY_BASE + 0x2100)362 #define DPIO_DATA (VLV_DISPLAY_BASE + 0x2104)363 #define DPIO_REG (VLV_DISPLAY_BASE + 0x2108)364 #define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)572 #define VLV_DISPLAY_BASE 0x180000 macro579 #define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)581 #define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)582 #define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)583 #define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)584 #define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)[all …]
296 .display_mmio_offset = VLV_DISPLAY_BASE,304 .display_mmio_offset = VLV_DISPLAY_BASE,
531 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE; in intel_setup_gmbus()
8581 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) in intel_setup_outputs()8582 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); in intel_setup_outputs()8584 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { in intel_setup_outputs()8585 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, in intel_setup_outputs()8587 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) in intel_setup_outputs()8588 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); in intel_setup_outputs()