| /drivers/net/wireless/ath/carl9170/ |
| D | debug.h | 100 u32 name##_sum[ARRAY_SIZE(name##_regs)], \
101 name##_counter[ARRAY_SIZE(name##_regs)] \
104 u32 name##_counter[ARRAY_SIZE(name##_regs)] \
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| D | debug.c | 475 u32 __tmp[ARRAY_SIZE(name##_regs)]; \
478 for (__i = 0; __i < ARRAY_SIZE(name##_regs); __i++) { \
479 __tmp[__i] = name##_regs[__i].reg; \
484 __err = carl9170_read_mreg(ar, ARRAY_SIZE(name##_regs), \
491 for (__i = 0; __i < ARRAY_SIZE(name##_regs); __i++) { \
504 max_len = ARRAY_SIZE(name##_regs) * 80; \
517 for (i = 0; i < ARRAY_SIZE(name##_regs); i++) { \
519 name##_regs[i].nreg, ar->debug.stats.name ##_sum[i],\
534 max_len = ARRAY_SIZE(name##_regs) * 80; \
545 for (i = 0; i < ARRAY_SIZE(name##_regs); i++) { \
[all …]
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| /drivers/clk/tegra/ |
| D | clk.h | 430 _div_flags, _clk_num, _enb_refcnt, _regs, \ argument
449 .regs = _regs, \
470 _div_width, _div_frac_width, _div_flags, _regs, \ argument
482 _enb_refcnt, _regs, \
492 _div_width, _div_frac_width, _div_flags, _regs, \ argument
497 _regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\
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| D | clk-tegra114.c | 661 _clk_num, _regs, _gate_flags, _clk_id) \ argument
663 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \
668 _clk_num, _regs, _gate_flags, _clk_id, flags)\ argument
670 30, MASK(2), 0, 0, 8, 1, 0, _regs, _clk_num, \
675 _clk_num, _regs, _gate_flags, _clk_id) \ argument
677 29, MASK(3), 0, 0, 8, 1, 0, _regs, _clk_num, \
682 _clk_num, _regs, _gate_flags, _clk_id) \ argument
684 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
689 _clk_num, _regs, _gate_flags, _clk_id, flags)\ argument
691 30, MASK(2), 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs,\
[all …]
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| D | clk-tegra30.c | 280 _clk_num, _regs, _gate_flags, _clk_id) \ argument
282 30, 2, 0, 0, 8, 1, 0, _regs, _clk_num, \
286 _clk_num, _regs, _gate_flags, _clk_id) \ argument
289 _regs, _clk_num, periph_clk_enb_refcnt, \
293 _clk_num, _regs, _gate_flags, _clk_id) \ argument
295 29, 3, 0, 0, 8, 1, 0, _regs, _clk_num, \
299 _clk_num, _regs, _gate_flags, _clk_id) \ argument
301 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
306 _clk_num, _regs, _clk_id) \ argument
308 30, 2, 0, 0, 16, 1, TEGRA_DIVIDER_UART, _regs, \
[all …]
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| D | clk-tegra20.c | 200 _clk_num, _regs, _gate_flags, _clk_id) \ argument
203 _regs, _clk_num, periph_clk_enb_refcnt, \
207 _clk_num, _regs, _gate_flags, _clk_id) \ argument
209 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT, _regs, \
214 _clk_num, _regs, _gate_flags, _clk_id) \ argument
216 30, 2, 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP, _regs, \
221 _mux_shift, _mux_width, _clk_num, _regs, \ argument
224 _mux_shift, _mux_width, 0, 0, 0, 0, 0, _regs, \
|