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Searched refs:bankw (Results 1 – 5 of 5) sorted by relevance

/drivers/gpu/drm/radeon/
Devergreen_cs.c172 unsigned bankw; member
264 palign = (8 * surf->bankw * track->npipes) * surf->mtilea; in evergreen_surface_check_2d()
343 switch (surf->bankw) { in evergreen_surface_value_conv_check()
344 case 0: surf->bankw = 1; break; in evergreen_surface_value_conv_check()
345 case 1: surf->bankw = 2; break; in evergreen_surface_value_conv_check()
346 case 2: surf->bankw = 4; break; in evergreen_surface_value_conv_check()
347 case 3: surf->bankw = 8; break; in evergreen_surface_value_conv_check()
350 __func__, __LINE__, prefix, surf->bankw); in evergreen_surface_value_conv_check()
406 surf.bankw = G_028C74_BANK_WIDTH(track->cb_color_attrib[id]); in evergreen_cs_track_validate_cb()
482 surf.bankw, surf.bankh, in evergreen_cs_track_validate_cb()
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Dradeon_object.c470 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; in radeon_bo_set_tiling_flags() local
472 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
477 switch (bankw) { in radeon_bo_set_tiling_flags()
Devergreen.c914 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, in evergreen_tiling_fields() argument
918 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in evergreen_tiling_fields()
922 switch (*bankw) { in evergreen_tiling_fields()
924 case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break; in evergreen_tiling_fields()
925 case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break; in evergreen_tiling_fields()
926 case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break; in evergreen_tiling_fields()
927 case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break; in evergreen_tiling_fields()
Datombios_crtc.c1073 unsigned bankw, bankh, mtaspect, tile_split; in dce4_crtc_do_set_base() local
1168 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1170 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw); in dce4_crtc_do_set_base()
Dradeon.h221 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,