| /drivers/scsi/ |
| D | nsp32_io.h | 12 static inline void nsp32_write1(unsigned int base, in nsp32_write1() argument
16 outb(val, (base + index)); in nsp32_write1()
19 static inline unsigned char nsp32_read1(unsigned int base, in nsp32_read1() argument
22 return inb(base + index); in nsp32_read1()
25 static inline void nsp32_write2(unsigned int base, in nsp32_write2() argument
29 outw(val, (base + index)); in nsp32_write2()
32 static inline unsigned short nsp32_read2(unsigned int base, in nsp32_read2() argument
35 return inw(base + index); in nsp32_read2()
38 static inline void nsp32_write4(unsigned int base, in nsp32_write4() argument
42 outl(val, (base + index)); in nsp32_write4()
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| D | aha1740.h | 18 #define HID0(base) (base + 0x0) argument
19 #define HID1(base) (base + 0x1) argument
20 #define HID2(base) (base + 0x2) argument
21 #define HID3(base) (base + 0x3) argument
22 #define EBCNTRL(base) (base + 0x4) argument
23 #define PORTADR(base) (base + 0x40) argument
24 #define BIOSADR(base) (base + 0x41) argument
25 #define INTDEF(base) (base + 0x42) argument
26 #define SCSIDEF(base) (base + 0x43) argument
27 #define BUSDEF(base) (base + 0x44) argument
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| D | sym53c416.c | 213 int base; member
232 static void sym53c416_set_transfer_counter(int base, unsigned int len) in sym53c416_set_transfer_counter() argument
235 outb(len & 0x0000FF, base + TC_LOW); in sym53c416_set_transfer_counter()
236 outb((len & 0x00FF00) >> 8, base + TC_MID); in sym53c416_set_transfer_counter()
237 outb((len & 0xFF0000) >> 16, base + TC_HIGH); in sym53c416_set_transfer_counter()
243 static __inline__ unsigned int sym53c416_read(int base, unsigned char *buffer, unsigned int len) in sym53c416_read() argument
255 bytes_left = inb(base + PIO_FIFO_CNT); /* Number of bytes in the PIO FIFO */ in sym53c416_read()
258 insl(base + PIO_FIFO_1, buffer, bytes_left >> 2); in sym53c416_read()
266 *(buffer++) = inb(base + PIO_FIFO_1); in sym53c416_read()
272 while(time_before(jiffies, i) && (inb(base + PIO_INT_REG) & EMPTY) && timeout) in sym53c416_read()
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| D | eata_pio.c | 106 seq_printf(m, "Base IO : %#.4x\n", (u32) shost->base); in eata_pio_show_info()
164 unsigned long base; in eata_pio_int_handler() local
175 if (inb(sh->base + HA_RSTATUS) & HA_SBUSY) in eata_pio_int_handler()
185 base = cmd->device->host->base; in eata_pio_int_handler()
188 stat = inb(base + HA_RSTATUS); in eata_pio_int_handler()
200 insw(base + HA_RDATA, cmd->SCp.ptr, x); in eata_pio_int_handler()
204 zwickel = inw(base + HA_RDATA); in eata_pio_int_handler()
212 zwickel = inw(base + HA_RDATA); in eata_pio_int_handler()
223 outw(zwickel, base + HA_RDATA); in eata_pio_int_handler()
228 outsw(base + HA_RDATA, cmd->SCp.ptr, x); in eata_pio_int_handler()
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| /drivers/isdn/hardware/avm/ |
| D | avmcard.h | 219 static inline unsigned char b1outp(unsigned int base, in b1outp() argument
223 outb(value, base + offset); in b1outp()
224 return inb(base + B1_ANALYSE); in b1outp()
228 static inline int b1_rx_full(unsigned int base) in b1_rx_full() argument
230 return inb(base + B1_INSTAT) & 0x1; in b1_rx_full()
233 static inline unsigned char b1_get_byte(unsigned int base) in b1_get_byte() argument
236 while (!b1_rx_full(base) && time_before(jiffies, stop)); in b1_get_byte()
237 if (b1_rx_full(base)) in b1_get_byte()
238 return inb(base + B1_READ); in b1_get_byte()
239 printk(KERN_CRIT "b1lli(0x%x): rx not full after 1 second\n", base); in b1_get_byte()
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| /drivers/ata/ |
| D | pata_bf54x.c | 77 #define ATAPI_GET_CONTROL(base)\ argument
78 bfin_read16(base + ATAPI_OFFSET_CONTROL)
79 #define ATAPI_SET_CONTROL(base, val)\ argument
80 bfin_write16(base + ATAPI_OFFSET_CONTROL, val)
81 #define ATAPI_GET_STATUS(base)\ argument
82 bfin_read16(base + ATAPI_OFFSET_STATUS)
83 #define ATAPI_GET_DEV_ADDR(base)\ argument
84 bfin_read16(base + ATAPI_OFFSET_DEV_ADDR)
85 #define ATAPI_SET_DEV_ADDR(base, val)\ argument
86 bfin_write16(base + ATAPI_OFFSET_DEV_ADDR, val)
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| /drivers/net/ethernet/broadcom/bnx2x/ |
| D | bnx2x_fw_defs.h | 13 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[148].base)
15 (IRO[147].base + ((assertListEntry) * IRO[147].m1))
17 (IRO[153].base + (((pfId)>>1) * IRO[153].m1) + (((pfId)&1) * \
20 (IRO[154].base + (((pfId)>>1) * IRO[154].m1) + (((pfId)&1) * \
23 (IRO[159].base + ((funcId) * IRO[159].m1))
25 (IRO[149].base + ((funcId) * IRO[149].m1))
27 (IRO[139].base + ((hcIndex) * IRO[139].m1) + ((sbId) * IRO[139].m2))
29 (IRO[138].base + (((hcIndex)>>2) * IRO[138].m1) + (((hcIndex)&3) \
31 #define CSTORM_IGU_MODE_OFFSET (IRO[157].base)
33 (IRO[317].base + ((pfId) * IRO[317].m1))
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| /drivers/gpio/ |
| D | gpio-samsung.c | 46 void __iomem *reg = chip->base + 0x08; in samsung_gpio_setpull_updown()
61 void __iomem *reg = chip->base + 0x08; in samsung_gpio_getpull_updown()
115 void __iomem *reg = chip->base + 0x08; in s3c24xx_gpio_setpull_1()
133 void __iomem *reg = chip->base + 0x08; in s3c24xx_gpio_getpull_1()
203 void __iomem *reg = chip->base; in samsung_gpio_setcfg_2bit()
238 con = __raw_readl(chip->base); in samsung_gpio_getcfg_2bit()
266 void __iomem *reg = chip->base; in samsung_gpio_setcfg_4bit()
301 void __iomem *reg = chip->base; in samsung_gpio_getcfg_4bit()
331 void __iomem *reg = chip->base; in s3c24xx_gpio_setcfg_abank()
371 con = __raw_readl(chip->base); in s3c24xx_gpio_getcfg_abank()
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| /drivers/s390/block/ |
| D | dasd_ioctl.c | 46 struct dasd_device *base; in dasd_ioctl_enable() local
51 base = dasd_device_from_gendisk(bdev->bd_disk); in dasd_ioctl_enable()
52 if (!base) in dasd_ioctl_enable()
55 dasd_enable_device(base); in dasd_ioctl_enable()
59 (loff_t)get_capacity(base->block->gdp) << 9); in dasd_ioctl_enable()
61 dasd_put_device(base); in dasd_ioctl_enable()
72 struct dasd_device *base; in dasd_ioctl_disable() local
77 base = dasd_device_from_gendisk(bdev->bd_disk); in dasd_ioctl_disable()
78 if (!base) in dasd_ioctl_disable()
88 dasd_set_target_state(base, DASD_STATE_BASIC); in dasd_ioctl_disable()
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| /drivers/irqchip/ |
| D | irq-vic.c | 72 void __iomem *base; member
98 static void vic_init2(void __iomem *base) in vic_init2() argument
103 void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4); in vic_init2()
107 writel(32, base + VIC_PL190_DEF_VECT_ADDR); in vic_init2()
113 void __iomem *base = vic->base; in resume_one_vic() local
115 printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base); in resume_one_vic()
118 vic_init2(base); in resume_one_vic()
120 writel(vic->int_select, base + VIC_INT_SELECT); in resume_one_vic()
121 writel(vic->protect, base + VIC_PROTECT); in resume_one_vic()
124 writel(vic->int_enable, base + VIC_INT_ENABLE); in resume_one_vic()
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| D | irq-sirfsoc.c | 31 sirfsoc_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num) in sirfsoc_alloc_gc() argument
36 gc = irq_alloc_generic_chip("SIRFINTC", 1, irq_start, base, handle_level_irq); in sirfsoc_alloc_gc()
48 void __iomem *base = sirfsoc_irqdomain->host_data; in sirfsoc_handle_irq() local
51 irqstat = readl_relaxed(base + SIRFSOC_INIT_IRQ_ID); in sirfsoc_handle_irq()
59 void __iomem *base = of_iomap(np, 0); in sirfsoc_irq_init() local
60 if (!base) in sirfsoc_irq_init()
65 &irq_domain_simple_ops, base); in sirfsoc_irq_init()
67 sirfsoc_alloc_gc(base, 0, 32); in sirfsoc_irq_init()
68 sirfsoc_alloc_gc(base + 4, 32, SIRFSOC_NUM_IRQS - 32); in sirfsoc_irq_init()
70 writel_relaxed(0, base + SIRFSOC_INT_RISC_LEVEL0); in sirfsoc_irq_init()
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| /drivers/gpu/drm/nouveau/core/engine/fifo/ |
| D | nv84.c | 50 struct nv50_fifo_base *base = (void *)parent->parent; in nv84_fifo_context_attach() local
66 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; in nv84_fifo_context_attach()
67 nv_wo32(base->eng, addr + 0x00, 0x00190000); in nv84_fifo_context_attach()
68 nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); in nv84_fifo_context_attach()
69 nv_wo32(base->eng, addr + 0x08, lower_32_bits(start)); in nv84_fifo_context_attach()
70 nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 | in nv84_fifo_context_attach()
72 nv_wo32(base->eng, addr + 0x10, 0x00000000); in nv84_fifo_context_attach()
73 nv_wo32(base->eng, addr + 0x14, 0x00000000); in nv84_fifo_context_attach()
84 struct nv50_fifo_base *base = (void *)parent->parent; in nv84_fifo_context_detach() local
100 nv_wr32(priv, 0x0032fc, nv_gpuobj(base)->addr >> 12); in nv84_fifo_context_detach()
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| D | nv50.c | 53 for (i = priv->base.min, p = 0; i < priv->base.max; i++) { in nv50_fifo_playlist_update_locked()
78 struct nv50_fifo_base *base = (void *)parent->parent; in nv50_fifo_context_attach() local
92 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; in nv50_fifo_context_attach()
93 nv_wo32(base->eng, addr + 0x00, 0x00190000); in nv50_fifo_context_attach()
94 nv_wo32(base->eng, addr + 0x04, lower_32_bits(limit)); in nv50_fifo_context_attach()
95 nv_wo32(base->eng, addr + 0x08, lower_32_bits(start)); in nv50_fifo_context_attach()
96 nv_wo32(base->eng, addr + 0x0c, upper_32_bits(limit) << 24 | in nv50_fifo_context_attach()
98 nv_wo32(base->eng, addr + 0x10, 0x00000000); in nv50_fifo_context_attach()
99 nv_wo32(base->eng, addr + 0x14, 0x00000000); in nv50_fifo_context_attach()
110 struct nv50_fifo_base *base = (void *)parent->parent; in nv50_fifo_context_detach() local
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| D | nvc0.c | 43 struct nouveau_fifo base; member
54 struct nouveau_fifo_base base; member
60 struct nouveau_fifo_chan base; member
99 struct nvc0_fifo_base *base = (void *)parent->parent; in nvc0_fifo_context_attach() local
117 ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, in nvc0_fifo_context_attach()
122 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; in nvc0_fifo_context_attach()
125 nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); in nvc0_fifo_context_attach()
126 nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset)); in nvc0_fifo_context_attach()
137 struct nvc0_fifo_base *base = (void *)parent->parent; in nvc0_fifo_context_detach() local
153 nv_wr32(priv, 0x002634, chan->base.chid); in nvc0_fifo_context_detach()
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| D | nve0.c | 64 struct nouveau_fifo base; member
74 struct nouveau_fifo_base base; member
80 struct nouveau_fifo_chan base; member
113 for (i = 0, p = 0; i < priv->base.max; i++) { in nve0_fifo_playlist_update()
135 struct nve0_fifo_base *base = (void *)parent->parent; in nve0_fifo_context_attach() local
153 ret = nouveau_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, in nve0_fifo_context_attach()
158 nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; in nve0_fifo_context_attach()
161 nv_wo32(base, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); in nve0_fifo_context_attach()
162 nv_wo32(base, addr + 0x04, upper_32_bits(ectx->vma.offset)); in nve0_fifo_context_attach()
173 struct nve0_fifo_base *base = (void *)parent->parent; in nve0_fifo_context_detach() local
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| /drivers/block/ |
| D | swim.c | 66 #define swim_write(base, reg, v) out_8(&(base)->write_##reg, (v)) argument
67 #define swim_read(base, reg) in_8(&(base)->read_##reg) argument
90 #define iwm_write(base, reg, v) out_8(&(base)->reg, (v)) argument
91 #define iwm_read(base, reg) in_8(&(base)->reg) argument
212 struct swim __iomem *base; member
219 extern int swim_read_sector_header(struct swim __iomem *base,
221 extern int swim_read_sector_data(struct swim __iomem *base,
225 static inline void set_swim_mode(struct swim __iomem *base, int enable) in set_swim_mode() argument
231 swim_write(base, mode0, 0xf8); in set_swim_mode()
235 iwm_base = (struct iwm __iomem *)base; in set_swim_mode()
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| /drivers/dma/ |
| D | ste_dma40.c | 282 void *base; member
338 void *base; member
418 struct d40_base *base; member
561 return chan->base->virtbase + D40_DREG_PCBASE + in chan_base()
576 void *base; in d40_pool_lli_alloc() local
584 base = d40d->lli_pool.pre_alloc_lli; in d40_pool_lli_alloc()
586 d40d->lli_pool.base = NULL; in d40_pool_lli_alloc()
590 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT); in d40_pool_lli_alloc()
591 d40d->lli_pool.base = base; in d40_pool_lli_alloc()
593 if (d40d->lli_pool.base == NULL) in d40_pool_lli_alloc()
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| /drivers/usb/phy/ |
| D | phy-mv-u3d-usb.c | 32 void __iomem *base; member
35 static u32 mv_u3d_phy_read(void __iomem *base, u32 reg) in mv_u3d_phy_read() argument
39 addr = base; in mv_u3d_phy_read()
40 data = base + 0x4; in mv_u3d_phy_read()
46 static void mv_u3d_phy_set(void __iomem *base, u32 reg, u32 value) in mv_u3d_phy_set() argument
51 addr = base; in mv_u3d_phy_set()
52 data = base + 0x4; in mv_u3d_phy_set()
60 static void mv_u3d_phy_clear(void __iomem *base, u32 reg, u32 value) in mv_u3d_phy_clear() argument
65 addr = base; in mv_u3d_phy_clear()
66 data = base + 0x4; in mv_u3d_phy_clear()
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| D | phy-tegra-usb.c | 230 void __iomem *base = phy->pad_regs; in utmip_pad_power_on() local
237 val = readl(base + UTMIP_BIAS_CFG0); in utmip_pad_power_on()
239 writel(val, base + UTMIP_BIAS_CFG0); in utmip_pad_power_on()
250 void __iomem *base = phy->pad_regs; in utmip_pad_power_off() local
262 val = readl(base + UTMIP_BIAS_CFG0); in utmip_pad_power_off()
264 writel(val, base + UTMIP_BIAS_CFG0); in utmip_pad_power_off()
289 void __iomem *base = phy->regs; in utmi_phy_clk_disable() local
292 val = readl(base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
294 writel(val, base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
298 val = readl(base + USB_SUSP_CTRL); in utmi_phy_clk_disable()
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| /drivers/scsi/pcmcia/ |
| D | nsp_io.h | 15 static inline void nsp_write(unsigned int base,
18 static inline unsigned char nsp_read(unsigned int base,
30 static inline void nsp_write(unsigned int base, in nsp_write() argument
34 outb(val, (base + index)); in nsp_write()
37 static inline unsigned char nsp_read(unsigned int base, in nsp_read() argument
40 return inb(base + index); in nsp_read()
75 static inline void nsp_fifo8_read(unsigned int base, in nsp_fifo8_read() argument
80 nsp_multi_read_1(base, FIFODATA, buf, count); in nsp_fifo8_read()
94 static inline void nsp_fifo16_read(unsigned int base, in nsp_fifo16_read() argument
99 nsp_multi_read_2(base, FIFODATA, buf, count); in nsp_fifo16_read()
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| /drivers/tty/ |
| D | isicom.c | 141 #define InterruptTheCard(base) outw(0, (base) + 0xc) argument
142 #define ClearInterrupt(base) inw((base) + 0x0a) argument
189 unsigned long base; member
223 static inline int WaitTillCardIsFree(unsigned long base) in WaitTillCardIsFree() argument
228 while (!(inw(base + 0xe) & 0x1) && count++ < 100) in WaitTillCardIsFree()
234 return !(inw(base + 0xe) & 0x1); in WaitTillCardIsFree()
239 unsigned long base = card->base; in lock_card() local
245 if (inw(base + 0xe) & 0x1) in lock_card()
252 pr_warning("Failed to lock Card (0x%lx)\n", card->base); in lock_card()
270 unsigned long base = card->base; in raise_dtr() local
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| /drivers/iommu/ |
| D | msm_iommu.c | 114 SET_CTX_TLBIALL(iommu_drvdata->base, ctx_drvdata->num, 0); in __flush_iotlb()
121 static void __reset_context(void __iomem *base, int ctx) in __reset_context() argument
123 SET_BPRCOSH(base, ctx, 0); in __reset_context()
124 SET_BPRCISH(base, ctx, 0); in __reset_context()
125 SET_BPRCNSH(base, ctx, 0); in __reset_context()
126 SET_BPSHCFG(base, ctx, 0); in __reset_context()
127 SET_BPMTCFG(base, ctx, 0); in __reset_context()
128 SET_ACTLR(base, ctx, 0); in __reset_context()
129 SET_SCTLR(base, ctx, 0); in __reset_context()
130 SET_FSRRESTORE(base, ctx, 0); in __reset_context()
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| D | msm_iommu_dev.c | 88 static void msm_iommu_reset(void __iomem *base, int ncb) in msm_iommu_reset() argument
92 SET_RPUE(base, 0); in msm_iommu_reset()
93 SET_RPUEIE(base, 0); in msm_iommu_reset()
94 SET_ESRRESTORE(base, 0); in msm_iommu_reset()
95 SET_TBE(base, 0); in msm_iommu_reset()
96 SET_CR(base, 0); in msm_iommu_reset()
97 SET_SPDMBE(base, 0); in msm_iommu_reset()
98 SET_TESTBUSCR(base, 0); in msm_iommu_reset()
99 SET_TLBRSW(base, 0); in msm_iommu_reset()
100 SET_GLOBAL_TLBIALL(base, 0); in msm_iommu_reset()
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| /drivers/mtd/chips/ |
| D | cfi_probe.c | 27 static int cfi_probe_chip(struct map_info *map, __u32 base,
38 #define xip_allowed(base, map) \ argument
40 (void) map_read(map, base); \
45 #define xip_enable(base, map, cfi) \ argument
47 cfi_qry_mode_off(base, map, cfi); \
48 xip_allowed(base, map); \
51 #define xip_disable_qry(base, map, cfi) \ argument
54 cfi_qry_mode_on(base, map, cfi); \
60 #define xip_allowed(base, map) do { } while (0) argument
61 #define xip_enable(base, map, cfi) do { } while (0) argument
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| /drivers/ide/ |
| D | palm_bk3710.c | 77 static void palm_bk3710_setudmamode(void __iomem *base, unsigned int dev, in palm_bk3710_setudmamode() argument
92 val32 = readl(base + BK3710_UDMASTB) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setudmamode()
94 writel(val32, base + BK3710_UDMASTB); in palm_bk3710_setudmamode()
97 val32 = readl(base + BK3710_UDMATRP) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setudmamode()
99 writel(val32, base + BK3710_UDMATRP); in palm_bk3710_setudmamode()
102 val32 = readl(base + BK3710_UDMAENV) & (0xFF << (dev ? 0 : 8)); in palm_bk3710_setudmamode()
104 writel(val32, base + BK3710_UDMAENV); in palm_bk3710_setudmamode()
107 val16 = readw(base + BK3710_UDMACTL) | (1 << dev); in palm_bk3710_setudmamode()
108 writew(val16, base + BK3710_UDMACTL); in palm_bk3710_setudmamode()
111 static void palm_bk3710_setdmamode(void __iomem *base, unsigned int dev, in palm_bk3710_setdmamode() argument
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