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Searched refs:byteout (Results 1 – 23 of 23) sorted by relevance

/drivers/isdn/hisax/
Davm_a1p.c56 #define byteout(addr, val) outb(val, addr) macro
67 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_REG_OFFSET + offset); in ReadISAC()
76 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_REG_OFFSET + offset); in WriteISAC()
77 byteout(cs->hw.avm.cfg_reg + DATAREG_OFFSET, value); in WriteISAC()
83 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_FIFO_OFFSET); in ReadISACfifo()
90 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, ISAC_FIFO_OFFSET); in WriteISACfifo()
100 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, in ReadHSCX()
110 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, in WriteHSCX()
112 byteout(cs->hw.avm.cfg_reg + DATAREG_OFFSET, value); in WriteHSCX()
118 byteout(cs->hw.avm.cfg_reg + ADDRREG_OFFSET, in ReadHSCXfifo()
[all …]
Dnj_u.c87 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in reset_netjet_u()
91 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in reset_netjet_u()
95 byteout(cs->hw.njet.auxa, 0); in reset_netjet_u()
96 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ); in reset_netjet_u()
97 byteout(cs->hw.njet.base + NETJET_IRQMASK1, NETJET_ISACIRQ); in reset_netjet_u()
98 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); in reset_netjet_u()
157 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in nju_cs_init()
161 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in nju_cs_init()
167 byteout(cs->hw.njet.auxa, 0); in nju_cs_init()
168 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ); in nju_cs_init()
[all …]
Dteleint.c21 #define byteout(addr, val) outb(val, addr) macro
30 byteout(ale, off); in readreg()
49 byteout(ale, off); in readfifo()
69 byteout(ale, off); in writereg()
77 byteout(adr, data); in writereg()
87 byteout(ale, off); in writefifo()
96 byteout(adr, data[i]); in writefifo()
137 byteout(cs->hw.hfc.addr | 1, reg); in ReadHFC()
149 byteout(cs->hw.hfc.addr | 1, reg); in WriteHFC()
152 byteout(cs->hw.hfc.addr, value); in WriteHFC()
[all …]
Dnj_s.c61 byteout(cs->hw.njet.base + NETJET_IRQSTAT0, s0val); in netjet_s_interrupt()
104 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in reset_netjet_s()
112 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in reset_netjet_s()
116 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ); in reset_netjet_s()
117 byteout(cs->hw.njet.base + NETJET_IRQMASK1, NETJET_ISACIRQ); in reset_netjet_s()
118 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); in reset_netjet_s()
196 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in njs_cs_init()
200 byteout(cs->hw.njet.base + NETJET_CTRL, cs->hw.njet.ctrl_reg); in njs_cs_init()
206 byteout(cs->hw.njet.base + NETJET_AUXCTRL, ~NETJET_ISACIRQ); in njs_cs_init()
207 byteout(cs->hw.njet.base + NETJET_IRQMASK1, NETJET_ISACIRQ); in njs_cs_init()
[all …]
Dsaphir.c23 #define byteout(addr, val) outb(val, addr) macro
38 byteout(ale, off); in readreg()
46 byteout(ale, off); in readfifo()
54 byteout(ale, off); in writereg()
55 byteout(adr, data); in writereg()
61 byteout(ale, off); in writefifo()
176 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, 0xff); in release_io_saphir()
207 byteout(cs->hw.saphir.cfg_reg + IRQ_REG, irq_val); in saphir_reset()
208 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 1); in saphir_reset()
210 byteout(cs->hw.saphir.cfg_reg + RESET_REG, 0); in saphir_reset()
[all …]
Delsa.c44 #define byteout(addr, val) outb(val, addr) macro
146 byteout(ale, off); in readreg()
154 byteout(ale, off); in readfifo()
162 byteout(ale, off); in writereg()
163 byteout(adr, data); in writereg()
169 byteout(ale, off); in writefifo()
242 byteout(cs->hw.elsa.ale, off); in readitac()
250 byteout(cs->hw.elsa.ale, off); in writeitac()
251 byteout(cs->hw.elsa.itac, data); in writeitac()
339 byteout(cs->hw.elsa.timer, 0); in elsa_interrupt()
[all …]
Davm_a1.c25 #define byteout(addr, val) outb(val, addr) macro
37 byteout(adr + off, data); in writereg()
112 byteout(cs->hw.avm.cfg_reg, 0x1E); in avm_a1_interrupt()
169 byteout(cs->hw.avm.cfg_reg, 0x16); in AVM_card_msg()
170 byteout(cs->hw.avm.cfg_reg, 0x1E); in AVM_card_msg()
251 byteout(cs->hw.avm.cfg_reg, 0x0); in setup_avm_a1()
253 byteout(cs->hw.avm.cfg_reg, 0x1); in setup_avm_a1()
255 byteout(cs->hw.avm.cfg_reg, 0x0); in setup_avm_a1()
260 byteout(cs->hw.avm.cfg_reg + 1, val); in setup_avm_a1()
262 byteout(cs->hw.avm.cfg_reg, 0x0); in setup_avm_a1()
Dsedlbauer.c83 #define byteout(addr, val) outb(val, addr) macro
124 byteout(ale, off); in readreg()
132 byteout(ale, off); in readfifo()
140 byteout(ale, off); in writereg()
141 byteout(adr, data); in writereg()
147 byteout(ale, off); in writefifo()
227 byteout(cs->hw.sedl.adr, offset); in ReadISAR()
238 byteout(cs->hw.sedl.adr, offset); in WriteISAR()
239 byteout(cs->hw.sedl.hscx, value); in WriteISAR()
427 byteout(cs->hw.sedl.cfg_reg + 3, cs->hw.sedl.reset_on); in reset_sedlbauer()
[all …]
Dsportster.c23 #define byteout(addr, val) outb(val, addr) macro
62 byteout(calc_off(cs->hw.spt.isac, offset), value); in WriteISAC()
86 byteout(calc_off(cs->hw.spt.hscx[hscx], offset), value); in WriteHSCX()
94 #define WRITEHSCX(cs, nr, reg, data) byteout(calc_off(cs->hw.spt.hscx[nr], reg), data)
139 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, 0); in release_io_sportster()
150 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq); in reset_sportster()
153 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq); in reset_sportster()
176 byteout(cs->hw.spt.cfg_reg + SPORTSTER_RES_IRQ, cs->hw.spt.res_irq); in Sportster_card_msg()
Dix1_micro.c29 #define byteout(addr, val) outb(val, addr) macro
46 byteout(ale, off); in readreg()
54 byteout(ale, off); in readfifo()
62 byteout(ale, off); in writereg()
63 byteout(adr, data); in writereg()
69 byteout(ale, off); in writefifo()
179 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 1); in ix1_reset()
182 byteout(cs->hw.ix1.cfg_reg + SPECIAL_PORT_OFFSET, 0); in ix1_reset()
Dmic.c21 #define byteout(addr, val) outb(val, addr) macro
36 byteout(ale, off); in readreg()
44 byteout(ale, off); in readfifo()
52 byteout(ale, off); in writereg()
53 byteout(adr, data); in writereg()
59 byteout(ale, off); in writefifo()
Dteles3.c25 #define byteout(addr, val) outb(val, addr) macro
37 byteout(adr + off, data); in writereg()
209 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg); in reset_teles3()
211 byteout(cs->hw.teles3.cfg_reg + 4, irqcfg | 1); in reset_teles3()
214 byteout(cs->hw.teles3.cfg_reg, 0xff); in reset_teles3()
216 byteout(cs->hw.teles3.cfg_reg, 0x00); in reset_teles3()
220 byteout(cs->hw.teles3.isac + 0x3c, 0); in reset_teles3()
222 byteout(cs->hw.teles3.isac + 0x3c, 1); in reset_teles3()
Dasuscom.c25 #define byteout(addr, val) outb(val, addr) macro
48 byteout(ale, off); in readreg()
56 byteout(ale, off); in readfifo()
64 byteout(ale, off); in writereg()
65 byteout(adr, data); in writereg()
71 byteout(ale, off); in writefifo()
255 byteout(cs->hw.asus.adr, ASUS_RESET); /* Reset On */ in reset_asuscom()
260 byteout(cs->hw.asus.adr, 0); /* Reset Off */ in reset_asuscom()
Dniccy.c26 #define byteout(addr, val) outb(val, addr) macro
50 byteout(ale, off); in readreg()
58 byteout(ale, off); in readfifo()
65 byteout(ale, off); in writereg()
66 byteout(adr, data); in writereg()
72 byteout(ale, off); in writefifo()
Dnetjet.c37 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); in NETjet_ReadIC()
47 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); in NETjet_WriteIC()
48 byteout(cs->hw.njet.isac + ((offset & 0xf) << 2), value); in NETjet_WriteIC()
55 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); in NETjet_ReadICfifo()
63 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); in NETjet_WriteICfifo()
108 byteout(cs->hw.njet.base + NETJET_DMACTRL, in mode_tiger()
110 byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0); in mode_tiger()
119 byteout(cs->hw.njet.auxa, cs->hw.njet.auxd); in mode_tiger()
138 byteout(cs->hw.njet.base + NETJET_DMACTRL, in mode_tiger()
140 byteout(cs->hw.njet.base + NETJET_IRQMASK0, 0x0f); in mode_tiger()
[all …]
Dgazel.c41 #define byteout(addr, val) outb(val, addr) macro
53 byteout(adr + off, data); in writereg()
74 byteout(adr, off); in readreg_ipac()
82 byteout(adr, off); in writereg_ipac()
83 byteout(adr + 4, data); in writereg_ipac()
90 byteout(adr, off); in read_fifo_ipac()
97 byteout(adr, off); in write_fifo_ipac()
Ddiva.c30 #define byteout(addr, val) outb(val, addr) macro
86 byteout(ale, off); in readreg()
94 byteout(ale, off); in readfifo()
102 byteout(ale, off); in writereg()
103 byteout(adr, data); in writereg()
109 byteout(ale, off); in writefifo()
725 byteout(cs->hw.diva.ctrl, 0); /* LED off, Reset */ in release_io_diva()
780 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg); in reset_diva()
783 byteout(cs->hw.diva.ctrl, cs->hw.diva.ctrl_reg); in reset_diva()
789 byteout(cs->hw.diva.pci_cfg + 0x69, 9); in reset_diva()
[all …]
Disurf.c22 #define byteout(addr, val) outb(val, addr) macro
136 byteout(cs->hw.isurf.reset, chips); /* Reset On */ in reset_isurf()
138 byteout(cs->hw.isurf.reset, ISURF_ISAR_EA); /* Reset Off */ in reset_isurf()
Dhfc_sx.c55 #define byteout(addr, val) outb(val, addr) macro
64 byteout(cs->hw.hfcsx.base + 1, regnum); in Write_hfc()
65 byteout(cs->hw.hfcsx.base, val); in Write_hfc()
73 byteout(cs->hw.hfcsx.base + 1, regnum); in Read_hfc()
88 byteout(cs->hw.hfcsx.base + 1, HFCSX_FIF_SEL); in fifo_select()
89 byteout(cs->hw.hfcsx.base, fifo); in fifo_select()
92 byteout(cs->hw.hfcsx.base, fifo); in fifo_select()
104 byteout(cs->hw.hfcsx.base + 1, HFCSX_CIRM); in reset_fifo()
105 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */ in reset_fifo()
1457 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF); in setup_hfcsx()
[all …]
Dteles0.c27 #define byteout(addr, val) outb(val, addr) macro
229 byteout(cs->hw.teles0.cfg_reg + 4, cfval); in reset_teles0()
231 byteout(cs->hw.teles0.cfg_reg + 4, cfval | 1); in reset_teles0()
Dnetjet.h15 #define byteout(addr, val) outb(val, addr) macro
Dhfc_2bds0.c25 #define byteout(addr, val) outb(val, addr) macro
42 byteout(cs->hw.hfcD.addr | 1, reg); in ReadReg()
59 byteout(cs->hw.hfcD.addr | 1, reg); in WriteReg()
62 byteout(cs->hw.hfcD.addr, value); in WriteReg()
/drivers/isdn/hysdn/
Dboardergo.c28 #define byteout(addr, val) outb(val, addr) macro
140 byteout(card->iobase + PCI9050_INTR_REG, val); in ergo_stopcard()
142 byteout(card->iobase + PCI9050_USER_IO, PCI9050_E1_RESET); /* reset E1 processor */ in ergo_stopcard()
241 byteout(card->iobase + PCI9050_USER_IO, PCI9050_E1_RUN); /* start E1 processor */ in ergo_writebootimg()
356 byteout(card->iobase + PCI9050_INTR_REG, in ergo_waitpofready()