Searched refs:cg_sel (Results 1 – 3 of 3) sorted by relevance
| /drivers/clk/ux500/ |
| D | clk-prcmu.c | 22 u8 cg_sel; member
35 ret = prcmu_request_clock(clk->cg_sel, true); in clk_prcmu_prepare()
45 if (prcmu_request_clock(clk->cg_sel, false)) in clk_prcmu_unprepare()
81 return prcmu_clock_rate(clk->cg_sel); in clk_prcmu_recalc_rate()
88 return prcmu_round_clock_rate(clk->cg_sel, rate); in clk_prcmu_round_rate()
95 return prcmu_set_clock_rate(clk->cg_sel, rate); in clk_prcmu_set_rate()
115 err = prcmu_request_clock(clk->cg_sel, true); in clk_prcmu_opp_prepare()
131 if (prcmu_request_clock(clk->cg_sel, false)) { in clk_prcmu_opp_unprepare()
161 err = prcmu_request_clock(clk->cg_sel, true); in clk_prcmu_opp_volt_prepare()
176 if (prcmu_request_clock(clk->cg_sel, false)) { in clk_prcmu_opp_volt_unprepare()
[all …]
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| D | clk-prcc.c | 31 u32 cg_sel; member
41 writel(clk->cg_sel, (clk->base + PRCC_PCKEN)); in clk_prcc_pclk_enable()
42 while (!(readl(clk->base + PRCC_PCKSR) & clk->cg_sel)) in clk_prcc_pclk_enable()
53 writel(clk->cg_sel, (clk->base + PRCC_PCKDIS)); in clk_prcc_pclk_disable()
61 writel(clk->cg_sel, (clk->base + PRCC_KCKEN)); in clk_prcc_kclk_enable()
62 while (!(readl(clk->base + PRCC_KCKSR) & clk->cg_sel)) in clk_prcc_kclk_enable()
73 writel(clk->cg_sel, (clk->base + PRCC_KCKDIS)); in clk_prcc_kclk_disable()
98 u32 cg_sel, in clk_reg_prcc() argument
121 clk->cg_sel = cg_sel; in clk_reg_prcc()
148 u32 cg_sel, in clk_reg_prcc_pclk() argument
[all …]
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| D | clk.h | 20 u32 cg_sel,
26 u32 cg_sel,
31 u8 cg_sel,
37 u8 cg_sel,
42 u8 cg_sel,
48 u8 cg_sel,
53 u8 cg_sel,
58 u8 cg_sel,
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