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Searched refs:clk_div (Results 1 – 25 of 33) sorted by relevance

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/drivers/net/ethernet/xilinx/
Dll_temac_mdio.c63 int clk_div; in temac_mdio_setup() local
68 clk_div = 0x3f; /* worst-case default setting */ in temac_mdio_setup()
71 clk_div = (*bus_hz) / (2500 * 1000 * 2) - 1; in temac_mdio_setup()
72 if (clk_div < 1) in temac_mdio_setup()
73 clk_div = 1; in temac_mdio_setup()
74 if (clk_div > 0x3f) in temac_mdio_setup()
75 clk_div = 0x3f; in temac_mdio_setup()
81 temac_indirect_out32(lp, XTE_MC_OFFSET, 1 << 6 | clk_div); in temac_mdio_setup()
Dxilinx_axienet_mdio.c131 u32 clk_div, host_clock; in axienet_mdio_setup() local
168 clk_div = DEFAULT_CLOCK_DIVISOR; in axienet_mdio_setup()
177 clk_div = DEFAULT_CLOCK_DIVISOR; in axienet_mdio_setup()
182 clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1; in axienet_mdio_setup()
187 clk_div++; in axienet_mdio_setup()
190 "on %u Hz host clock.\n", __func__, clk_div, host_clock); in axienet_mdio_setup()
195 (((u32) clk_div) | XAE_MDIO_MC_MDIOEN_MASK)); in axienet_mdio_setup()
/drivers/clk/mxs/
Dclk-div.c28 struct clk_div { struct
35 static inline struct clk_div *to_clk_div(struct clk_hw *hw) in to_clk_div() argument
39 return container_of(divider, struct clk_div, divider); in to_clk_div()
45 struct clk_div *div = to_clk_div(hw); in clk_div_recalc_rate()
53 struct clk_div *div = to_clk_div(hw); in clk_div_round_rate()
61 struct clk_div *div = to_clk_div(hw); in clk_div_set_rate()
80 struct clk_div *div; in mxs_clk_div()
/drivers/pwm/
Dpwm-samsung.c32 struct clk *clk_div; member
52 return clk_get_parent(chip->clk) == chip->clk_div; in pwm_is_tdiv()
97 tin_parent_rate = clk_get_rate(clk_get_parent(s3c->clk_div)); in pwm_calc_tin()
149 clk_set_rate(s3c->clk_div, tin_rate); in s3c_pwm_config()
237 s3c->clk_div = devm_clk_get(dev, "pwm-tdiv"); in s3c_pwm_probe()
238 if (IS_ERR(s3c->clk_div)) { in s3c_pwm_probe()
240 return PTR_ERR(s3c->clk_div); in s3c_pwm_probe()
244 clk_enable(s3c->clk_div); in s3c_pwm_probe()
265 clk_get_rate(s3c->clk_div), in s3c_pwm_probe()
272 clk_disable(s3c->clk_div); in s3c_pwm_probe()
[all …]
/drivers/tty/serial/
Dmrst_max3110.c588 int clk_div = -1; in serial_m3110_set_termios() local
611 clk_div = WC_BAUD_DR384; in serial_m3110_set_termios()
614 clk_div = WC_BAUD_DR192; in serial_m3110_set_termios()
617 clk_div = WC_BAUD_DR96; in serial_m3110_set_termios()
620 clk_div = WC_BAUD_DR48; in serial_m3110_set_termios()
623 clk_div = WC_BAUD_DR24; in serial_m3110_set_termios()
626 clk_div = WC_BAUD_DR12; in serial_m3110_set_termios()
629 clk_div = WC_BAUD_DR6; in serial_m3110_set_termios()
632 clk_div = WC_BAUD_DR3; in serial_m3110_set_termios()
635 clk_div = WC_BAUD_DR2; in serial_m3110_set_termios()
[all …]
/drivers/mmc/host/
Dbfin_sdh.c74 unsigned int clk_div; member
145 cycle_ns = 1000000000 / (host->sclk / (2 * (host->clk_div + 1))); in sdh_setup_data()
429 unsigned char clk_div; in sdh_set_ios() local
430 clk_div = (get_sclk() / ios->clock - 1) / 2; in sdh_set_ios()
431 clk_div = min_t(unsigned char, clk_div, 0xFF); in sdh_set_ios()
432 clk_ctl |= clk_div; in sdh_set_ios()
434 host->clk_div = clk_div; in sdh_set_ios()
452 host->clk_div, in sdh_set_ios()
453 host->clk_div ? get_sclk() / (2 * (host->clk_div + 1)) : 0, in sdh_set_ios()
Dtifm_sd.c99 unsigned int clk_div; member
603 ((1000000000UL / host->clk_freq) * host->clk_div); in tifm_sd_set_data_timeout()
835 host->clk_div = clk_div1; in tifm_sd_ios()
841 host->clk_div = clk_div2; in tifm_sd_ios()
847 host->clk_div = 0; in tifm_sd_ios()
849 host->clk_div &= TIFM_MMCSD_CLKMASK; in tifm_sd_ios()
850 writel(host->clk_div in tifm_sd_ios()
892 host->clk_div = 61; in tifm_sd_initialize_host()
895 writel(host->clk_div | TIFM_MMCSD_POWER, in tifm_sd_initialize_host()
914 writel(host->clk_div | TIFM_MMCSD_POWER, in tifm_sd_initialize_host()
Ds3cmci.h32 unsigned long clk_div; member
Ds3cmci.c1289 host->real_rate = host->clk_rate / (host->clk_div*(mci_psc+1)); in s3cmci_set_clk()
1667 host->clk_div = 1; in s3cmci_probe()
1671 host->clk_div = 2; in s3cmci_probe()
1803 mmc->f_min = host->clk_rate / (host->clk_div * 256); in s3cmci_probe()
1804 mmc->f_max = host->clk_rate / host->clk_div; in s3cmci_probe()
/drivers/spi/
Dspi-dw.c60 u16 clk_div; /* baud rate divider */ member
387 u16 clk_div = 0; in pump_transfers() local
397 if (unlikely(!chip->clk_div)) in pump_transfers()
398 chip->clk_div = dws->max_freq / chip->speed_hz; in pump_transfers()
451 clk_div = dws->max_freq / speed; in pump_transfers()
452 clk_div = (clk_div + 1) & 0xfffe; in pump_transfers()
455 chip->clk_div = clk_div; in pump_transfers()
518 if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) { in pump_transfers()
524 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div); in pump_transfers()
Dspi-pxa2xx.c591 u32 clk_div = 0; in pump_transfers() local
685 clk_div = ssp_get_clk_div(drv_data, speed); in pump_transfers()
720 cr0 = clk_div in pump_transfers()
871 unsigned int clk_div; in setup() local
973 clk_div = ssp_get_clk_div(drv_data, spi->max_speed_hz); in setup()
976 chip->cr0 = clk_div in setup()
/drivers/staging/media/davinci_vpfe/
Ddm365_ipipeif.c317 val |= (params.if_5_1.clk_div.m - 1) << in ipipeif_hw_setup()
319 val |= (params.if_5_1.clk_div.n - 1); in ipipeif_hw_setup()
413 ipipeif->config.if_5_1.clk_div.m = config->if_5_1.clk_div.m; in ipipeif_set_config()
414 ipipeif->config.if_5_1.clk_div.n = config->if_5_1.clk_div.n; in ipipeif_set_config()
449 config->if_5_1.clk_div.m = ipipeif->config.if_5_1.clk_div.m; in ipipeif_get_config()
450 config->if_5_1.clk_div.n = ipipeif->config.if_5_1.clk_div.n; in ipipeif_get_config()
742 .clk_div = { in ipipeif_set_default_config()
Ddm365_ipipeif_user.h55 struct ipipeif_5_1_clkdiv clk_div; member
/drivers/media/dvb-frontends/
Dstv6110.c40 u8 clk_div; member
219 priv->regs[RSTV6110_CTRL2] |= (priv->clk_div << 6); in stv6110_init()
412 reg0[2] |= (config->clk_div << 6); in stv6110_attach()
432 priv->clk_div = config->clk_div; in stv6110_attach()
Dstv6110.h46 u8 clk_div; /* divisor value for the output clock */ member
Dstv6110x.h29 u8 clk_div; /* divisor value for the output clock */ member
/drivers/media/i2c/soc_camera/
Drj54n1cb0c.c154 struct rj54n1_clock_div clk_div; member
414 static const struct rj54n1_clock_div clk_div = { variable
825 rj54n1->clk_div.ratio_tg); in rj54n1_set_clock()
828 rj54n1->clk_div.ratio_t); in rj54n1_set_clock()
831 rj54n1->clk_div.ratio_r); in rj54n1_set_clock()
844 rj54n1->clk_div.ratio_op); in rj54n1_set_clock()
847 rj54n1->clk_div.ratio_o); in rj54n1_set_clock()
1373 rj54n1->clk_div = clk_div; in rj54n1_probe()
1383 (clk_div.ratio_tg + 1) / (clk_div.ratio_t + 1); in rj54n1_probe()
/drivers/video/omap/
Dsossi.c71 int clk_div; member
135 int div = t->clk_div; in calc_rd_timings()
186 int div = t->clk_div; in calc_wr_timings()
269 _set_timing(sossi.clk_div, in set_timing()
328 int div = t->clk_div; in sossi_convert_timings()
359 sossi.clk_div = t->tim[4]; in sossi_set_timings()
Domapfb.h116 int clk_div; member
/drivers/cpufreq/
Dexynos5440-cpufreq.c119 unsigned int tmp, clk_div, ema_div, freq, volt_id; in init_div_table() local
137 clk_div = ((freq / CPU_DIV_FREQ_MAX) & P0_7_CPUCLKDEV_MASK) in init_div_table()
139 clk_div |= ((freq / CPU_ATB_FREQ_MAX) & P0_7_ATBCLKDEV_MASK) in init_div_table()
141 clk_div |= ((freq / CPU_DBG_FREQ_MAX) & P0_7_CSCLKDEV_MASK) in init_div_table()
158 tmp = (clk_div | ema_div | (volt_id << P0_7_VDD_SHIFT) in init_div_table()
/drivers/staging/media/solo6x10/
Dsolo6x10-g723.c70 int clk_div; in solo_g723_config() local
72 clk_div = (solo_dev->clock_mhz * 1000000) in solo_g723_config()
77 | SOLO_AUDIO_CLK_DIV(clk_div)); in solo_g723_config()
/drivers/i2c/busses/
Di2c-sirf.c81 u32 clk_div; member
406 siic->clk_div = readl(siic->base + SIRFSOC_I2C_CLK_CTRL); in i2c_sirfsoc_suspend()
421 writel(siic->clk_div, siic->base + SIRFSOC_I2C_CLK_CTRL); in i2c_sirfsoc_resume()
/drivers/gpu/drm/shmobile/
Dshmob_drm_crtc.c188 if (idata->clk_div) { in shmob_drm_crtc_start()
193 lcdc_write(sdev, LDDCKPAT2R, (1 << (idata->clk_div / 2)) - 1); in shmob_drm_crtc_start()
195 if (idata->clk_div == 1) in shmob_drm_crtc_start()
198 value |= idata->clk_div; in shmob_drm_crtc_start()
/drivers/media/pci/ngene/
Dngene-cards.c607 .clk_div = 1,
613 .clk_div = 1,
/drivers/video/omap2/dss/
Drfbi.c401 t->clk_div = div; in calc_reg_timing()
493 int div = t->clk_div; in rfbi_convert_timings()

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