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Searched refs:crtc_offsets (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/radeon/
Drv515.c43 static const u32 crtc_offsets[2] = variable
300 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN; in rv515_mc_stop()
303 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop()
306 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in rv515_mc_stop()
308 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
309 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in rv515_mc_stop()
320 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in rv515_mc_stop()
321 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]); in rv515_mc_stop()
323 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp); in rv515_mc_stop()
324 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0); in rv515_mc_stop()
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Devergreen.c40 static const u32 crtc_offsets[6] = variable
1104 if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK) in dce4_is_in_vblank()
1114 pos1 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1115 pos2 = RREG32(EVERGREEN_CRTC_STATUS_POSITION + crtc_offsets[crtc]); in dce4_is_counter_moving()
1138 if (!(RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN)) in dce4_wait_for_vblank()
2355 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; in evergreen_mc_stop()
2359 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
2362 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + crtc_offsets[i], 1); in evergreen_mc_stop()
2364 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp); in evergreen_mc_stop()
2367 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]); in evergreen_mc_stop()
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Drs600.c49 static const u32 crtc_offsets[2] = variable
57 if (RREG32(AVIVO_D1CRTC_STATUS + crtc_offsets[crtc]) & AVIVO_D1CRTC_V_BLANK) in avivo_is_in_vblank()
67 pos1 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
68 pos2 = RREG32(AVIVO_D1CRTC_STATUS_POSITION + crtc_offsets[crtc]); in avivo_is_counter_moving()
91 if (!(RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[crtc]) & AVIVO_CRTC_EN)) in avivo_wait_for_vblank()
Dr600.c97 static const u32 crtc_offsets[2] = variable
1358 if (RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN) { in r600_is_display_hung()
1359 crtc_status[i] = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()
1367 tmp = RREG32(AVIVO_D1CRTC_STATUS_HV_COUNT + crtc_offsets[i]); in r600_is_display_hung()