Searched refs:div_mask (Results 1 – 5 of 5) sorted by relevance
33 #define div_mask(d) ((1 << ((d)->width)) - 1) macro49 return div_mask(divider); in _get_maxdiv()51 return 1 << div_mask(divider); in _get_maxdiv()54 return div_mask(divider) + 1; in _get_maxdiv()108 val &= div_mask(divider); in clk_divider_recalc_rate()214 if (value > div_mask(divider)) in clk_divider_set_rate()215 value = div_mask(divider); in clk_divider_set_rate()221 val &= ~(div_mask(divider) << divider->shift); in clk_divider_set_rate()
29 unsigned int div_mask; member108 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()111 if ((cdev->div_mask == 0x3F) && (div & BIT(5))) in vt8500_dclk_recalc_rate()116 div = (cdev->div_mask + 1); in vt8500_dclk_recalc_rate()140 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_round_rate()163 if (divisor == cdev->div_mask + 1) in vt8500_dclk_set_rate()167 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_set_rate()175 if (divisor > cdev->div_mask) { in vt8500_dclk_set_rate()253 dev_clk->div_mask = 0x1f; in vtwm_device_clk_init()255 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask); in vtwm_device_clk_init()
27 #define div_mask(d) ((1 << (d->width)) - 1) macro29 #define get_max_div(d) div_mask(d)76 div = reg & div_mask(divider); in clk_frac_div_recalc_rate()123 val &= ~(div_mask(divider) << divider->shift); in clk_frac_div_set_rate()
100 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; in sh_clk_div_recalc()116 value &= ~(clk->div_mask << clk->enable_bit); in sh_clk_div_set_rate()129 if (clk->div_mask == SH_CLK_DIV6_MSK) { in sh_clk_div_enable()152 val |= clk->div_mask; in sh_clk_div_disable()
521 u32 div_mask; member528 .div_mask = PRCM_DSITVCLK_DIV_DSI0_ESC_CLK_DIV_MASK,533 .div_mask = PRCM_DSITVCLK_DIV_DSI1_ESC_CLK_DIV_MASK,538 .div_mask = PRCM_DSITVCLK_DIV_DSI2_ESC_CLK_DIV_MASK,741 u32 div_mask; in prcmu_config_clkout() local752 div_mask = PRCM_CLKOCR_CLKODIV0_MASK; in prcmu_config_clkout()758 div_mask = PRCM_CLKOCR_CLKODIV1_MASK; in prcmu_config_clkout()770 if (val & div_mask) { in prcmu_config_clkout()777 if ((val & mask & ~div_mask) != bits) { in prcmu_config_clkout()1637 div = ((div & dsiescclk[n].div_mask) >> (dsiescclk[n].div_shift)); in dsiescclk_rate()[all …]