1 /* 2 * Linux MegaRAID driver for SAS based RAID controllers 3 * 4 * Copyright (c) 2009-2012 LSI Corporation. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 19 * 20 * FILE: megaraid_sas_fusion.h 21 * 22 * Authors: LSI Corporation 23 * Manoj Jose 24 * Sumant Patro 25 * 26 * Send feedback to: <megaraidlinux@lsi.com> 27 * 28 * Mail to: LSI Corporation, 1621 Barber Lane, Milpitas, CA 95035 29 * ATTN: Linuxraid 30 */ 31 32 #ifndef _MEGARAID_SAS_FUSION_H_ 33 #define _MEGARAID_SAS_FUSION_H_ 34 35 /* Fusion defines */ 36 #define MEGASAS_MAX_SZ_CHAIN_FRAME 1024 37 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 38 #define MEGA_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 39 #define MEGASAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 40 #define MEGASAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 41 #define MEGASAS_LOAD_BALANCE_FLAG 0x1 42 #define MEGASAS_DCMD_MBOX_PEND_FLAG 0x1 43 #define HOST_DIAG_WRITE_ENABLE 0x80 44 #define HOST_DIAG_RESET_ADAPTER 0x4 45 #define MEGASAS_FUSION_MAX_RESET_TRIES 3 46 #define MAX_MSIX_QUEUES_FUSION 16 47 48 /* Invader defines */ 49 #define MPI2_TYPE_CUDA 0x2 50 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 51 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 52 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 53 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 54 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 55 56 /* T10 PI defines */ 57 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8 58 #define MEGASAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 59 #define MEGASAS_SCSI_SERVICE_ACTION_READ32 0x9 60 #define MEGASAS_SCSI_SERVICE_ACTION_WRITE32 0xB 61 #define MEGASAS_SCSI_ADDL_CDB_LEN 0x18 62 #define MEGASAS_RD_WR_PROTECT_CHECK_ALL 0x20 63 #define MEGASAS_RD_WR_PROTECT_CHECK_NONE 0x60 64 65 /* 66 * Raid context flags 67 */ 68 69 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 70 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 71 enum MR_RAID_FLAGS_IO_SUB_TYPE { 72 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 73 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 74 }; 75 76 /* 77 * Request descriptor types 78 */ 79 #define MEGASAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 80 #define MEGASAS_REQ_DESCRIPT_FLAGS_MFA 0x1 81 #define MEGASAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 82 #define MEGASAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 83 84 #define MEGASAS_FP_CMD_LEN 16 85 #define MEGASAS_FUSION_IN_RESET 0 86 87 /* 88 * Raid Context structure which describes MegaRAID specific IO Paramenters 89 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 90 */ 91 92 struct RAID_CONTEXT { 93 u8 Type:4; 94 u8 nseg:4; 95 u8 resvd0; 96 u16 timeoutValue; 97 u8 regLockFlags; 98 u8 resvd1; 99 u16 VirtualDiskTgtId; 100 u64 regLockRowLBA; 101 u32 regLockLength; 102 u16 nextLMId; 103 u8 exStatus; 104 u8 status; 105 u8 RAIDFlags; 106 u8 numSGE; 107 u16 configSeqNum; 108 u8 spanArm; 109 u8 resvd2[3]; 110 }; 111 112 #define RAID_CTX_SPANARM_ARM_SHIFT (0) 113 #define RAID_CTX_SPANARM_ARM_MASK (0x1f) 114 115 #define RAID_CTX_SPANARM_SPAN_SHIFT (5) 116 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 117 118 /* 119 * define region lock types 120 */ 121 enum REGION_TYPE { 122 REGION_TYPE_UNUSED = 0, 123 REGION_TYPE_SHARED_READ = 1, 124 REGION_TYPE_SHARED_WRITE = 2, 125 REGION_TYPE_EXCLUSIVE = 3, 126 }; 127 128 /* MPI2 defines */ 129 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 130 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 131 #define MPI2_VERSION_MAJOR (0x02) 132 #define MPI2_VERSION_MINOR (0x00) 133 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 134 #define MPI2_VERSION_MAJOR_SHIFT (8) 135 #define MPI2_VERSION_MINOR_MASK (0x00FF) 136 #define MPI2_VERSION_MINOR_SHIFT (0) 137 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 138 MPI2_VERSION_MINOR) 139 #define MPI2_HEADER_VERSION_UNIT (0x10) 140 #define MPI2_HEADER_VERSION_DEV (0x00) 141 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 142 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 143 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 144 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 145 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | \ 146 MPI2_HEADER_VERSION_DEV) 147 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 148 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 149 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 150 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 151 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 152 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 153 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 154 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 155 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 156 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 157 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 158 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 159 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 160 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 161 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 162 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 163 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 164 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 165 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 166 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 167 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 168 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 169 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 170 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 171 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 172 173 struct MPI25_IEEE_SGE_CHAIN64 { 174 u64 Address; 175 u32 Length; 176 u16 Reserved1; 177 u8 NextChainOffset; 178 u8 Flags; 179 }; 180 181 struct MPI2_SGE_SIMPLE_UNION { 182 u32 FlagsLength; 183 union { 184 u32 Address32; 185 u64 Address64; 186 } u; 187 }; 188 189 struct MPI2_SCSI_IO_CDB_EEDP32 { 190 u8 CDB[20]; /* 0x00 */ 191 u32 PrimaryReferenceTag; /* 0x14 */ 192 u16 PrimaryApplicationTag; /* 0x18 */ 193 u16 PrimaryApplicationTagMask; /* 0x1A */ 194 u32 TransferLength; /* 0x1C */ 195 }; 196 197 struct MPI2_SGE_CHAIN_UNION { 198 u16 Length; 199 u8 NextChainOffset; 200 u8 Flags; 201 union { 202 u32 Address32; 203 u64 Address64; 204 } u; 205 }; 206 207 struct MPI2_IEEE_SGE_SIMPLE32 { 208 u32 Address; 209 u32 FlagsLength; 210 }; 211 212 struct MPI2_IEEE_SGE_CHAIN32 { 213 u32 Address; 214 u32 FlagsLength; 215 }; 216 217 struct MPI2_IEEE_SGE_SIMPLE64 { 218 u64 Address; 219 u32 Length; 220 u16 Reserved1; 221 u8 Reserved2; 222 u8 Flags; 223 }; 224 225 struct MPI2_IEEE_SGE_CHAIN64 { 226 u64 Address; 227 u32 Length; 228 u16 Reserved1; 229 u8 Reserved2; 230 u8 Flags; 231 }; 232 233 union MPI2_IEEE_SGE_SIMPLE_UNION { 234 struct MPI2_IEEE_SGE_SIMPLE32 Simple32; 235 struct MPI2_IEEE_SGE_SIMPLE64 Simple64; 236 }; 237 238 union MPI2_IEEE_SGE_CHAIN_UNION { 239 struct MPI2_IEEE_SGE_CHAIN32 Chain32; 240 struct MPI2_IEEE_SGE_CHAIN64 Chain64; 241 }; 242 243 union MPI2_SGE_IO_UNION { 244 struct MPI2_SGE_SIMPLE_UNION MpiSimple; 245 struct MPI2_SGE_CHAIN_UNION MpiChain; 246 union MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 247 union MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 248 }; 249 250 union MPI2_SCSI_IO_CDB_UNION { 251 u8 CDB32[32]; 252 struct MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 253 struct MPI2_SGE_SIMPLE_UNION SGE; 254 }; 255 256 /* 257 * RAID SCSI IO Request Message 258 * Total SGE count will be one less than _MPI2_SCSI_IO_REQUEST 259 */ 260 struct MPI2_RAID_SCSI_IO_REQUEST { 261 u16 DevHandle; /* 0x00 */ 262 u8 ChainOffset; /* 0x02 */ 263 u8 Function; /* 0x03 */ 264 u16 Reserved1; /* 0x04 */ 265 u8 Reserved2; /* 0x06 */ 266 u8 MsgFlags; /* 0x07 */ 267 u8 VP_ID; /* 0x08 */ 268 u8 VF_ID; /* 0x09 */ 269 u16 Reserved3; /* 0x0A */ 270 u32 SenseBufferLowAddress; /* 0x0C */ 271 u16 SGLFlags; /* 0x10 */ 272 u8 SenseBufferLength; /* 0x12 */ 273 u8 Reserved4; /* 0x13 */ 274 u8 SGLOffset0; /* 0x14 */ 275 u8 SGLOffset1; /* 0x15 */ 276 u8 SGLOffset2; /* 0x16 */ 277 u8 SGLOffset3; /* 0x17 */ 278 u32 SkipCount; /* 0x18 */ 279 u32 DataLength; /* 0x1C */ 280 u32 BidirectionalDataLength; /* 0x20 */ 281 u16 IoFlags; /* 0x24 */ 282 u16 EEDPFlags; /* 0x26 */ 283 u32 EEDPBlockSize; /* 0x28 */ 284 u32 SecondaryReferenceTag; /* 0x2C */ 285 u16 SecondaryApplicationTag; /* 0x30 */ 286 u16 ApplicationTagTranslationMask; /* 0x32 */ 287 u8 LUN[8]; /* 0x34 */ 288 u32 Control; /* 0x3C */ 289 union MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 290 struct RAID_CONTEXT RaidContext; /* 0x60 */ 291 union MPI2_SGE_IO_UNION SGL; /* 0x80 */ 292 }; 293 294 /* 295 * MPT RAID MFA IO Descriptor. 296 */ 297 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR { 298 u32 RequestFlags:8; 299 u32 MessageAddress1:24; /* bits 31:8*/ 300 u32 MessageAddress2; /* bits 61:32 */ 301 }; 302 303 /* Default Request Descriptor */ 304 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR { 305 u8 RequestFlags; /* 0x00 */ 306 u8 MSIxIndex; /* 0x01 */ 307 u16 SMID; /* 0x02 */ 308 u16 LMID; /* 0x04 */ 309 u16 DescriptorTypeDependent; /* 0x06 */ 310 }; 311 312 /* High Priority Request Descriptor */ 313 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 314 u8 RequestFlags; /* 0x00 */ 315 u8 MSIxIndex; /* 0x01 */ 316 u16 SMID; /* 0x02 */ 317 u16 LMID; /* 0x04 */ 318 u16 Reserved1; /* 0x06 */ 319 }; 320 321 /* SCSI IO Request Descriptor */ 322 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 323 u8 RequestFlags; /* 0x00 */ 324 u8 MSIxIndex; /* 0x01 */ 325 u16 SMID; /* 0x02 */ 326 u16 LMID; /* 0x04 */ 327 u16 DevHandle; /* 0x06 */ 328 }; 329 330 /* SCSI Target Request Descriptor */ 331 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 332 u8 RequestFlags; /* 0x00 */ 333 u8 MSIxIndex; /* 0x01 */ 334 u16 SMID; /* 0x02 */ 335 u16 LMID; /* 0x04 */ 336 u16 IoIndex; /* 0x06 */ 337 }; 338 339 /* RAID Accelerator Request Descriptor */ 340 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 341 u8 RequestFlags; /* 0x00 */ 342 u8 MSIxIndex; /* 0x01 */ 343 u16 SMID; /* 0x02 */ 344 u16 LMID; /* 0x04 */ 345 u16 Reserved; /* 0x06 */ 346 }; 347 348 /* union of Request Descriptors */ 349 union MEGASAS_REQUEST_DESCRIPTOR_UNION { 350 struct MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 351 struct MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 352 struct MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 353 struct MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 354 struct MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 355 struct MEGASAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 356 union { 357 struct { 358 u32 low; 359 u32 high; 360 } u; 361 u64 Words; 362 }; 363 }; 364 365 /* Default Reply Descriptor */ 366 struct MPI2_DEFAULT_REPLY_DESCRIPTOR { 367 u8 ReplyFlags; /* 0x00 */ 368 u8 MSIxIndex; /* 0x01 */ 369 u16 DescriptorTypeDependent1; /* 0x02 */ 370 u32 DescriptorTypeDependent2; /* 0x04 */ 371 }; 372 373 /* Address Reply Descriptor */ 374 struct MPI2_ADDRESS_REPLY_DESCRIPTOR { 375 u8 ReplyFlags; /* 0x00 */ 376 u8 MSIxIndex; /* 0x01 */ 377 u16 SMID; /* 0x02 */ 378 u32 ReplyFrameAddress; /* 0x04 */ 379 }; 380 381 /* SCSI IO Success Reply Descriptor */ 382 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 383 u8 ReplyFlags; /* 0x00 */ 384 u8 MSIxIndex; /* 0x01 */ 385 u16 SMID; /* 0x02 */ 386 u16 TaskTag; /* 0x04 */ 387 u16 Reserved1; /* 0x06 */ 388 }; 389 390 /* TargetAssist Success Reply Descriptor */ 391 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 392 u8 ReplyFlags; /* 0x00 */ 393 u8 MSIxIndex; /* 0x01 */ 394 u16 SMID; /* 0x02 */ 395 u8 SequenceNumber; /* 0x04 */ 396 u8 Reserved1; /* 0x05 */ 397 u16 IoIndex; /* 0x06 */ 398 }; 399 400 /* Target Command Buffer Reply Descriptor */ 401 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 402 u8 ReplyFlags; /* 0x00 */ 403 u8 MSIxIndex; /* 0x01 */ 404 u8 VP_ID; /* 0x02 */ 405 u8 Flags; /* 0x03 */ 406 u16 InitiatorDevHandle; /* 0x04 */ 407 u16 IoIndex; /* 0x06 */ 408 }; 409 410 /* RAID Accelerator Success Reply Descriptor */ 411 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 412 u8 ReplyFlags; /* 0x00 */ 413 u8 MSIxIndex; /* 0x01 */ 414 u16 SMID; /* 0x02 */ 415 u32 Reserved; /* 0x04 */ 416 }; 417 418 /* union of Reply Descriptors */ 419 union MPI2_REPLY_DESCRIPTORS_UNION { 420 struct MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 421 struct MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 422 struct MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 423 struct MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 424 struct MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 425 struct MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 426 RAIDAcceleratorSuccess; 427 u64 Words; 428 }; 429 430 /* IOCInit Request message */ 431 struct MPI2_IOC_INIT_REQUEST { 432 u8 WhoInit; /* 0x00 */ 433 u8 Reserved1; /* 0x01 */ 434 u8 ChainOffset; /* 0x02 */ 435 u8 Function; /* 0x03 */ 436 u16 Reserved2; /* 0x04 */ 437 u8 Reserved3; /* 0x06 */ 438 u8 MsgFlags; /* 0x07 */ 439 u8 VP_ID; /* 0x08 */ 440 u8 VF_ID; /* 0x09 */ 441 u16 Reserved4; /* 0x0A */ 442 u16 MsgVersion; /* 0x0C */ 443 u16 HeaderVersion; /* 0x0E */ 444 u32 Reserved5; /* 0x10 */ 445 u16 Reserved6; /* 0x14 */ 446 u8 Reserved7; /* 0x16 */ 447 u8 HostMSIxVectors; /* 0x17 */ 448 u16 Reserved8; /* 0x18 */ 449 u16 SystemRequestFrameSize; /* 0x1A */ 450 u16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 451 u16 ReplyFreeQueueDepth; /* 0x1E */ 452 u32 SenseBufferAddressHigh; /* 0x20 */ 453 u32 SystemReplyAddressHigh; /* 0x24 */ 454 u64 SystemRequestFrameBaseAddress; /* 0x28 */ 455 u64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 456 u64 ReplyFreeQueueAddress; /* 0x38 */ 457 u64 TimeStamp; /* 0x40 */ 458 }; 459 460 /* mrpriv defines */ 461 #define MR_PD_INVALID 0xFFFF 462 #define MAX_SPAN_DEPTH 8 463 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 464 #define MAX_ROW_SIZE 32 465 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 466 #define MAX_LOGICAL_DRIVES 64 467 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 468 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 469 #define MAX_ARRAYS 128 470 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 471 #define MAX_PHYSICAL_DEVICES 256 472 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 473 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 474 475 struct MR_DEV_HANDLE_INFO { 476 u16 curDevHdl; 477 u8 validHandles; 478 u8 reserved; 479 u16 devHandle[2]; 480 }; 481 482 struct MR_ARRAY_INFO { 483 u16 pd[MAX_RAIDMAP_ROW_SIZE]; 484 }; 485 486 struct MR_QUAD_ELEMENT { 487 u64 logStart; 488 u64 logEnd; 489 u64 offsetInSpan; 490 u32 diff; 491 u32 reserved1; 492 }; 493 494 struct MR_SPAN_INFO { 495 u32 noElements; 496 u32 reserved1; 497 struct MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; 498 }; 499 500 struct MR_LD_SPAN { 501 u64 startBlk; 502 u64 numBlks; 503 u16 arrayRef; 504 u8 reserved[6]; 505 }; 506 507 struct MR_SPAN_BLOCK_INFO { 508 u64 num_rows; 509 struct MR_LD_SPAN span; 510 struct MR_SPAN_INFO block_span_info; 511 }; 512 513 struct MR_LD_RAID { 514 struct { 515 u32 fpCapable:1; 516 u32 reserved5:3; 517 u32 ldPiMode:4; 518 u32 pdPiMode:4; 519 u32 encryptionType:8; 520 u32 fpWriteCapable:1; 521 u32 fpReadCapable:1; 522 u32 fpWriteAcrossStripe:1; 523 u32 fpReadAcrossStripe:1; 524 u32 reserved4:8; 525 } capability; 526 u32 reserved6; 527 u64 size; 528 u8 spanDepth; 529 u8 level; 530 u8 stripeShift; 531 u8 rowSize; 532 u8 rowDataSize; 533 u8 writeMode; 534 u8 PRL; 535 u8 SRL; 536 u16 targetId; 537 u8 ldState; 538 u8 regTypeReqOnWrite; 539 u8 modFactor; 540 u8 regTypeReqOnRead; 541 u16 seqNum; 542 543 struct { 544 u32 ldSyncRequired:1; 545 u32 reserved:31; 546 } flags; 547 548 u8 reserved3[0x5C]; 549 }; 550 551 struct MR_LD_SPAN_MAP { 552 struct MR_LD_RAID ldRaid; 553 u8 dataArmMap[MAX_RAIDMAP_ROW_SIZE]; 554 struct MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; 555 }; 556 557 struct MR_FW_RAID_MAP { 558 u32 totalSize; 559 union { 560 struct { 561 u32 maxLd; 562 u32 maxSpanDepth; 563 u32 maxRowSize; 564 u32 maxPdCount; 565 u32 maxArrays; 566 } validationInfo; 567 u32 version[5]; 568 u32 reserved1[5]; 569 }; 570 571 u32 ldCount; 572 u32 Reserved1; 573 u8 ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES+ 574 MAX_RAIDMAP_VIEWS]; 575 u8 fpPdIoTimeoutSec; 576 u8 reserved2[7]; 577 struct MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; 578 struct MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 579 struct MR_LD_SPAN_MAP ldSpanMap[1]; 580 }; 581 582 struct IO_REQUEST_INFO { 583 u64 ldStartBlock; 584 u32 numBlocks; 585 u16 ldTgtId; 586 u8 isRead; 587 u16 devHandle; 588 u64 pdBlock; 589 u8 fpOkForIo; 590 }; 591 592 struct MR_LD_TARGET_SYNC { 593 u8 targetId; 594 u8 reserved; 595 u16 seqNum; 596 }; 597 598 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 599 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 600 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 601 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 602 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 603 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 604 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 605 606 struct megasas_register_set; 607 struct megasas_instance; 608 609 union desc_word { 610 u64 word; 611 struct { 612 u32 low; 613 u32 high; 614 } u; 615 }; 616 617 struct megasas_cmd_fusion { 618 struct MPI2_RAID_SCSI_IO_REQUEST *io_request; 619 dma_addr_t io_request_phys_addr; 620 621 union MPI2_SGE_IO_UNION *sg_frame; 622 dma_addr_t sg_frame_phys_addr; 623 624 u8 *sense; 625 dma_addr_t sense_phys_addr; 626 627 struct list_head list; 628 struct scsi_cmnd *scmd; 629 struct megasas_instance *instance; 630 631 u8 retry_for_fw_reset; 632 union MEGASAS_REQUEST_DESCRIPTOR_UNION *request_desc; 633 634 /* 635 * Context for a MFI frame. 636 * Used to get the mfi cmd from list when a MFI cmd is completed 637 */ 638 u32 sync_cmd_idx; 639 u32 index; 640 u8 flags; 641 }; 642 643 struct LD_LOAD_BALANCE_INFO { 644 u8 loadBalanceFlag; 645 u8 reserved1; 646 u16 raid1DevHandle[2]; 647 atomic_t scsi_pending_cmds[2]; 648 u64 last_accessed_block[2]; 649 }; 650 651 struct MR_FW_RAID_MAP_ALL { 652 struct MR_FW_RAID_MAP raidMap; 653 struct MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 654 } __attribute__ ((packed)); 655 656 struct fusion_context { 657 struct megasas_cmd_fusion **cmd_list; 658 struct list_head cmd_pool; 659 660 spinlock_t cmd_pool_lock; 661 662 dma_addr_t req_frames_desc_phys; 663 u8 *req_frames_desc; 664 665 struct dma_pool *io_request_frames_pool; 666 dma_addr_t io_request_frames_phys; 667 u8 *io_request_frames; 668 669 struct dma_pool *sg_dma_pool; 670 struct dma_pool *sense_dma_pool; 671 672 dma_addr_t reply_frames_desc_phys; 673 union MPI2_REPLY_DESCRIPTORS_UNION *reply_frames_desc; 674 struct dma_pool *reply_frames_desc_pool; 675 676 u16 last_reply_idx[MAX_MSIX_QUEUES_FUSION]; 677 678 u32 reply_q_depth; 679 u32 request_alloc_sz; 680 u32 reply_alloc_sz; 681 u32 io_frames_alloc_sz; 682 683 u16 max_sge_in_main_msg; 684 u16 max_sge_in_chain; 685 686 u8 chain_offset_io_request; 687 u8 chain_offset_mfi_pthru; 688 689 struct MR_FW_RAID_MAP_ALL *ld_map[2]; 690 dma_addr_t ld_map_phys[2]; 691 692 u32 map_sz; 693 u8 fast_path_io; 694 struct LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES]; 695 }; 696 697 union desc_value { 698 u64 word; 699 struct { 700 u32 low; 701 u32 high; 702 } u; 703 }; 704 705 #endif /* _MEGARAID_SAS_FUSION_H_ */ 706