| /drivers/gpu/drm/radeon/ |
| D | radeon_clocks.c | 38 uint32_t fb_div, ref_div, post_div, sclk; in radeon_legacy_get_engine_clock() local
40 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_get_engine_clock()
41 fb_div = (fb_div >> RADEON_SPLL_FB_DIV_SHIFT) & RADEON_SPLL_FB_DIV_MASK; in radeon_legacy_get_engine_clock()
42 fb_div <<= 1; in radeon_legacy_get_engine_clock()
43 fb_div *= spll->reference_freq; in radeon_legacy_get_engine_clock()
51 sclk = fb_div / ref_div; in radeon_legacy_get_engine_clock()
68 uint32_t fb_div, ref_div, post_div, mclk; in radeon_legacy_get_memory_clock() local
70 fb_div = RREG32_PLL(RADEON_M_SPLL_REF_FB_DIV); in radeon_legacy_get_memory_clock()
71 fb_div = (fb_div >> RADEON_MPLL_FB_DIV_SHIFT) & RADEON_MPLL_FB_DIV_MASK; in radeon_legacy_get_memory_clock()
72 fb_div <<= 1; in radeon_legacy_get_memory_clock()
[all …]
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| D | radeon_display.c | 743 u32 *fb_div, in avivo_get_fb_div() argument
749 *fb_div = tmp / pll->reference_freq; in avivo_get_fb_div()
752 if (*fb_div > pll->max_feedback_div) in avivo_get_fb_div()
753 *fb_div = pll->max_feedback_div; in avivo_get_fb_div()
754 else if (*fb_div < pll->min_feedback_div) in avivo_get_fb_div()
755 *fb_div = pll->min_feedback_div; in avivo_get_fb_div()
810 u32 fb_div = 0, frac_fb_div = 0, tmp; in radeon_compute_pll_avivo() local
816 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div); in radeon_compute_pll_avivo()
824 fb_div++; in radeon_compute_pll_avivo()
830 &fb_div, &frac_fb_div); in radeon_compute_pll_avivo()
[all …]
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| D | radeon_uvd.c | 771 uint64_t fb_div = (uint64_t)vco_freq * fb_factor; in radeon_uvd_calc_upll_dividers() local
774 do_div(fb_div, ref_freq); in radeon_uvd_calc_upll_dividers()
777 if (fb_div > fb_mask) in radeon_uvd_calc_upll_dividers()
780 fb_div &= fb_mask; in radeon_uvd_calc_upll_dividers()
799 *optimal_fb_div = fb_div; in radeon_uvd_calc_upll_dividers()
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| D | atombios_crtc.c | 772 u32 fb_div, in atombios_crtc_program_pll() argument
799 args.v1.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
809 args.v2.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
819 args.v3.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
836 args.v5.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
858 args.v6.usFbDiv = cpu_to_le16(fb_div); in atombios_crtc_program_pll()
996 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; in atombios_crtc_set_pll() local
1022 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1025 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
1028 &fb_div, &frac_fb_div, &ref_div, &post_div); in atombios_crtc_set_pll()
[all …]
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| D | rv770.c | 49 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in rv770_set_uvd_clocks() local
69 &fb_div, &vclk_div, &dclk_div); in rv770_set_uvd_clocks()
73 fb_div |= 1; in rv770_set_uvd_clocks()
103 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), in rv770_set_uvd_clocks()
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| D | radeon_legacy_crtc.c | 263 uint16_t fb_div) in radeon_compute_pll_gain() argument
270 vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; in radeon_compute_pll_gain()
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| D | radeon_mode.h | 508 u32 fb_div; member
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| D | radeon_atombios.c | 2697 dividers->fb_div = args.v1.ucFbDiv; in radeon_atom_get_clock_dividers()
2710 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv); in radeon_atom_get_clock_dividers()
2717 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false; in radeon_atom_get_clock_dividers()
2729 dividers->fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv); in radeon_atom_get_clock_dividers()
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| D | evergreen.c | 995 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in evergreen_set_uvd_clocks() local
1014 &fb_div, &vclk_div, &dclk_div); in evergreen_set_uvd_clocks()
1041 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in evergreen_set_uvd_clocks()
1046 if (fb_div < 307200) in evergreen_set_uvd_clocks()
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| D | si.c | 5650 unsigned fb_div = 0, vclk_div = 0, dclk_div = 0; in si_set_uvd_clocks() local
5669 &fb_div, &vclk_div, &dclk_div); in si_set_uvd_clocks()
5699 WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div), ~UPLL_FB_DIV_MASK); in si_set_uvd_clocks()
5704 if (fb_div < 307200) in si_set_uvd_clocks()
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| /drivers/video/aty/ |
| D | radeon_base.c | 1435 int fb_div, pll_output_freq = 0; in radeon_calc_pll_regs() local
1524 fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, in radeon_calc_pll_regs()
1527 regs->ppll_div_3 = fb_div | (post_div->bitvalue << 16); in radeon_calc_pll_regs()
1530 pr_debug("fb_div = 0x%x\n", fb_div); in radeon_calc_pll_regs()
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