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Searched refs:hdisplay (Results 1 – 25 of 76) sorted by relevance

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/drivers/gpu/drm/
Ddrm_modes.c56 mode->hdisplay, mode->hsync_start, in drm_mode_debug_printmodeline()
87 struct drm_display_mode *drm_cvt_mode(struct drm_device *dev, int hdisplay, in drm_cvt_mode() argument
124 hdisplay_rnd = hdisplay - (hdisplay % CVT_H_GRANULARITY); in drm_cvt_mode()
133 drm_mode->hdisplay = hdisplay_rnd + 2 * hmargin; in drm_cvt_mode()
155 if (!(vdisplay % 3) && ((vdisplay * 4 / 3) == hdisplay)) in drm_cvt_mode()
157 else if (!(vdisplay % 9) && ((vdisplay * 16 / 9) == hdisplay)) in drm_cvt_mode()
159 else if (!(vdisplay % 10) && ((vdisplay * 16 / 10) == hdisplay)) in drm_cvt_mode()
161 else if (!(vdisplay % 4) && ((vdisplay * 5 / 4) == hdisplay)) in drm_cvt_mode()
163 else if (!(vdisplay % 9) && ((vdisplay * 15 / 9) == hdisplay)) in drm_cvt_mode()
215 hblank = drm_mode->hdisplay * hblank_percentage / in drm_cvt_mode()
[all …]
Ddrm_edid.c1274 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay)
1326 return (mode->htotal - mode->hdisplay == 160) && in mode_is_rb()
1327 (mode->hsync_end - mode->hdisplay == 80) && in mode_is_rb()
1351 if (hsize != ptr->hdisplay) in drm_mode_find_dmt()
1577 if (m->hdisplay == hsize && m->vdisplay == vsize && in drm_mode_std()
1585 mode->hdisplay = 1366; in drm_mode_std()
1665 if ((mode->hdisplay == cea_interlaced[i].w) && in drm_mode_do_interlace_quirk()
1740 mode->hdisplay = hactive; in drm_mode_detailed()
1741 mode->hsync_start = mode->hdisplay + hsync_offset; in drm_mode_detailed()
1743 mode->htotal = mode->hdisplay + hblank; in drm_mode_detailed()
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/drivers/gpu/drm/i915/
Dintel_panel.c42 adjusted_mode->hdisplay = fixed_mode->hdisplay; in intel_fixed_panel_mode()
68 if (adjusted_mode->hdisplay == mode->hdisplay && in intel_pch_panel_fitting()
74 width = mode->hdisplay; in intel_pch_panel_fitting()
76 x = (adjusted_mode->hdisplay - width + 1)/2; in intel_pch_panel_fitting()
83 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; in intel_pch_panel_fitting()
84 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; in intel_pch_panel_fitting()
89 x = (adjusted_mode->hdisplay - width + 1) / 2; in intel_pch_panel_fitting()
93 height = scaled_width / mode->hdisplay; in intel_pch_panel_fitting()
98 width = adjusted_mode->hdisplay; in intel_pch_panel_fitting()
101 width = adjusted_mode->hdisplay; in intel_pch_panel_fitting()
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Dintel_lvds.c236 if (mode->hdisplay > fixed_mode->hdisplay) in intel_lvds_mode_valid()
255 border = (mode->hdisplay - width + 1) / 2; in centre_horizontally()
355 if (adjusted_mode->hdisplay == mode->hdisplay && in intel_lvds_compute_config()
382 centre_horizontally(adjusted_mode, mode->hdisplay); in intel_lvds_compute_config()
390 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; in intel_lvds_compute_config()
391 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; in intel_lvds_compute_config()
398 else if (adjusted_mode->hdisplay != mode->hdisplay) in intel_lvds_compute_config()
401 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; in intel_lvds_compute_config()
402 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; in intel_lvds_compute_config()
421 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay); in intel_lvds_compute_config()
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Ddvo_ns2501.c280 __FUNCTION__, mode->hdisplay, mode->htotal, mode->vdisplay, in ns2501_mode_valid()
289 if ((mode->hdisplay == 800 && mode->vdisplay == 600) || in ns2501_mode_valid()
290 (mode->hdisplay == 640 && mode->vdisplay == 480) || in ns2501_mode_valid()
291 (mode->hdisplay == 1024 && mode->vdisplay == 768)) { in ns2501_mode_valid()
308 __FUNCTION__, mode->hdisplay, mode->htotal, mode->vdisplay, in ns2501_mode_set()
320 if (mode->hdisplay == 800 && mode->vdisplay == 600) { in ns2501_mode_set()
385 } else if (mode->hdisplay == 640 && mode->vdisplay == 480) { in ns2501_mode_set()
450 } else if (mode->hdisplay == 1024 && mode->vdisplay == 768) { in ns2501_mode_set()
Ddvo_ch7017.c301 horizontal_active_pixel_input = mode->hdisplay & 0x00ff; in ch7017_mode_set()
304 horizontal_active_pixel_output = mode->hdisplay & 0x00ff; in ch7017_mode_set()
306 active_input_line_output = ((mode->hdisplay & 0x0700) >> 8) | in ch7017_mode_set()
310 (mode->hdisplay & 0x0700) >> 8; in ch7017_mode_set()
Ddvo_ivch.c351 if (mode->hdisplay != adjusted_mode->hdisplay || in ivch_mode_set()
357 x_ratio = (((mode->hdisplay - 1) << 16) / in ivch_mode_set()
358 (adjusted_mode->hdisplay - 1)) >> 2; in ivch_mode_set()
/drivers/gpu/drm/gma500/
Dmdfld_tpo_vid.c42 mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo; in tpo_vid_get_config_mode()
44 mode->hsync_start = mode->hdisplay + in tpo_vid_get_config_mode()
50 mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | in tpo_vid_get_config_mode()
62 dev_dbg(dev->dev, "hdisplay is %d\n", mode->hdisplay); in tpo_vid_get_config_mode()
72 mode->hdisplay = 864; in tpo_vid_get_config_mode()
Dmdfld_tmd_vid.c45 mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo; in tmd_vid_get_config_mode()
47 mode->hsync_start = mode->hdisplay + \ in tmd_vid_get_config_mode()
53 mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \ in tmd_vid_get_config_mode()
65 dev_dbg(dev->dev, "hdisplay is %d\n", mode->hdisplay); in tmd_vid_get_config_mode()
75 mode->hdisplay = 480; in tmd_vid_get_config_mode()
Doaktrail_lvds.c145 (mode->hdisplay != adjusted_mode->crtc_hdisplay)) { in oaktrail_lvds_mode_set()
147 (mode->hdisplay * adjusted_mode->crtc_vdisplay)) in oaktrail_lvds_mode_set()
150 mode->vdisplay) > (mode->hdisplay * in oaktrail_lvds_mode_set()
265 mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo; in oaktrail_lvds_get_configuration_mode()
267 mode->hsync_start = mode->hdisplay + \ in oaktrail_lvds_get_configuration_mode()
273 mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \ in oaktrail_lvds_get_configuration_mode()
285 printk(KERN_INFO "hdisplay is %d\n", mode->hdisplay); in oaktrail_lvds_get_configuration_mode()
Dcdv_intel_lvds.c264 if (mode->hdisplay > fixed_mode->hdisplay) in cdv_intel_lvds_mode_valid()
300 adjusted_mode->hdisplay = panel_fixed_mode->hdisplay; in cdv_intel_lvds_mode_fixup()
374 if (mode->hdisplay != adjusted_mode->hdisplay || in cdv_intel_lvds_mode_set()
495 if (crtc->saved_mode.hdisplay != 0 && in cdv_intel_lvds_set_property()
Dpsb_intel_lvds.c369 if (mode->hdisplay > fixed_mode->hdisplay) in psb_intel_lvds_mode_valid()
421 adjusted_mode->hdisplay = panel_fixed_mode->hdisplay; in psb_intel_lvds_mode_fixup()
493 if (mode->hdisplay != adjusted_mode->hdisplay || in psb_intel_lvds_mode_set()
619 if (crtc->saved_mode.hdisplay != 0 && in psb_intel_lvds_set_property()
Dmdfld_dsi_dpi.c435 pclk_hactive = mode->hdisplay; in mdfld_dsi_dpi_timing_calculation()
436 pclk_hfp = mode->hsync_start - mode->hdisplay; in mdfld_dsi_dpi_timing_calculation()
519 mode->vdisplay << 16 | mode->hdisplay); in mdfld_dsi_dpi_controller_init()
696 adjusted_mode->hdisplay = fixed_mode->hdisplay; in mdfld_dsi_dpi_mode_fixup()
753 mode->vdisplay << 16 | mode->hdisplay); in mdfld_mipi_set_video_timing()
797 REG_WRITE(HTOTAL_A, ((mode->htotal - 1) << 16) | (mode->hdisplay - 1)); in mdfld_set_pipe_timing()
798 REG_WRITE(HBLANK_A, ((mode->htotal - 1) << 16) | (mode->hdisplay - 1)); in mdfld_set_pipe_timing()
808 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1)); in mdfld_set_pipe_timing()
873 ((mode->vdisplay - 1) << 16) | (mode->hdisplay - 1)); in mdfld_dsi_dpi_mode_set()
/drivers/gpu/drm/nouveau/dispnv04/
Dtvnv17.c220 for (tv_mode = nv17_tv_modes; tv_mode->hdisplay; tv_mode++) { in nv17_tv_get_ld_modes()
232 if (mode->hdisplay == tv_norm->tv_enc_mode.hdisplay && in nv17_tv_get_ld_modes()
250 int hdisplay; in nv17_tv_get_hd_modes() member
266 if (modes[i].hdisplay > output_mode->hdisplay || in nv17_tv_get_hd_modes()
270 if (modes[i].hdisplay == output_mode->hdisplay && in nv17_tv_get_hd_modes()
276 mode = drm_cvt_mode(encoder->dev, modes[i].hdisplay, in nv17_tv_get_hd_modes()
283 if (output_mode->hdisplay <= 720 in nv17_tv_get_hd_modes()
284 || output_mode->hdisplay >= 1920) { in nv17_tv_get_hd_modes()
286 mode->hsync_start = (mode->hdisplay + (mode->htotal in nv17_tv_get_hd_modes()
287 - mode->hdisplay) * 9 / 10) & ~7; in nv17_tv_get_hd_modes()
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Ddfp.c191 mode->hdisplay > nv_connector->native_mode->hdisplay || in nv04_dfp_mode_fixup()
299 regp->fp_horiz_regs[FP_DISPLAY_END] = output_mode->hdisplay - 1; in nv04_dfp_mode_set()
302 (output_mode->hsync_start - output_mode->hdisplay) >= in nv04_dfp_mode_set()
304 regp->fp_horiz_regs[FP_CRTC] = output_mode->hdisplay; in nv04_dfp_mode_set()
310 regp->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - 1; in nv04_dfp_mode_set()
333 else if (adjusted_mode->hdisplay == output_mode->hdisplay && in nv04_dfp_mode_set()
373 mode_ratio = (1 << 12) * adjusted_mode->hdisplay / adjusted_mode->vdisplay; in nv04_dfp_mode_set()
374 panel_ratio = (1 << 12) * output_mode->hdisplay / output_mode->vdisplay; in nv04_dfp_mode_set()
392 diff = output_mode->hdisplay - in nv04_dfp_mode_set()
403 scale = (1 << 12) * adjusted_mode->hdisplay / output_mode->hdisplay; in nv04_dfp_mode_set()
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Dtvmodesnv17.c326 uint64_t rs[] = {mode->hdisplay * id3, in tv_setup_filter()
329 do_div(rs[0], overscan * tv_norm->tv_enc_mode.hdisplay); in tv_setup_filter()
560 hmargin = (output_mode->hdisplay - crtc_mode->hdisplay) / 2; in nv17_ctv_update_rescaler()
563 hmargin = interpolate(0, min(hmargin, output_mode->hdisplay/20), in nv17_ctv_update_rescaler()
568 hratio = crtc_mode->hdisplay * 0x800 / in nv17_ctv_update_rescaler()
569 (output_mode->hdisplay - 2*hmargin); in nv17_ctv_update_rescaler()
574 regs->fp_horiz_regs[FP_VALID_END] = output_mode->hdisplay - hmargin - 1; in nv17_ctv_update_rescaler()
/drivers/gpu/drm/radeon/
Dradeon_encoders.c284 unsigned hblank = native_mode->htotal - native_mode->hdisplay; in radeon_panel_mode_fixup()
286 unsigned hover = native_mode->hsync_start - native_mode->hdisplay; in radeon_panel_mode_fixup()
295 adjusted_mode->hdisplay = native_mode->hdisplay; in radeon_panel_mode_fixup()
299 adjusted_mode->htotal = native_mode->hdisplay + hblank; in radeon_panel_mode_fixup()
300 adjusted_mode->hsync_start = native_mode->hdisplay + hover; in radeon_panel_mode_fixup()
310 adjusted_mode->crtc_hdisplay = native_mode->hdisplay; in radeon_panel_mode_fixup()
Dradeon_connectors.c294 if (native_mode->hdisplay != 0 && in radeon_fp_native_mode()
302 } else if (native_mode->hdisplay != 0 && in radeon_fp_native_mode()
311 mode = drm_cvt_mode(dev, native_mode->hdisplay, native_mode->vdisplay, 60, true, false, false); in radeon_fp_native_mode()
355 if (common_modes[i].w > native_mode->hdisplay || in radeon_add_common_modes()
357 (common_modes[i].w == native_mode->hdisplay && in radeon_add_common_modes()
514 if (mode->hdisplay != native_mode->hdisplay || in radeon_fixup_lvds_native_mode()
523 if (mode->hdisplay == native_mode->hdisplay && in radeon_fixup_lvds_native_mode()
583 if ((mode->hdisplay < 320) || (mode->vdisplay < 240)) in radeon_lvds_mode_valid()
593 if ((mode->hdisplay > native_mode->hdisplay) || in radeon_lvds_mode_valid()
599 if ((mode->hdisplay != native_mode->hdisplay) || in radeon_lvds_mode_valid()
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/drivers/staging/imx-drm/
Dipuv3-crtc.c84 return mode->hdisplay * mode->vdisplay * vref; in calc_bandwidth()
208 mode->hdisplay); in ipu_crtc_mode_set()
245 sig_cfg.width = mode->hdisplay; in ipu_crtc_mode_set()
250 sig_cfg.h_end_width = mode->hsync_start - mode->hdisplay; in ipu_crtc_mode_set()
276 out_pixel_fmt, mode->hdisplay); in ipu_crtc_mode_set()
291 ipu_cpmem_set_resolution(cpmem, mode->hdisplay, mode->vdisplay); in ipu_crtc_mode_set()
295 ret = ipu_dmfc_init_channel(ipu_crtc->dmfc, mode->hdisplay); in ipu_crtc_mode_set()
/drivers/gpu/drm/omapdrm/
Domap_connector.c42 mode->hdisplay = timings->x_res; in copy_timings_omap_to_drm()
43 mode->hsync_start = mode->hdisplay + timings->hfp; in copy_timings_omap_to_drm()
73 timings->x_res = mode->hdisplay; in copy_timings_drm_to_omap()
74 timings->hfp = mode->hsync_start - mode->hdisplay; in copy_timings_drm_to_omap()
234 mode->hdisplay, mode->hsync_start, in omap_connector_mode_valid()
Domap_crtc.c212 mode->hdisplay, mode->hsync_start, in omap_crtc_mode_set()
222 0, 0, mode->hdisplay, mode->vdisplay, in omap_crtc_mode_set()
224 mode->hdisplay << 16, mode->vdisplay << 16, in omap_crtc_mode_set()
250 0, 0, mode->hdisplay, mode->vdisplay, in omap_crtc_mode_set_base()
252 mode->hdisplay << 16, mode->vdisplay << 16, in omap_crtc_mode_set_base()
289 0, 0, mode->hdisplay, mode->vdisplay, in page_flip_worker()
291 mode->hdisplay << 16, mode->vdisplay << 16, in page_flip_worker()
/drivers/gpu/drm/nouveau/
Dnouveau_connector.c590 if (mode->hdisplay < high_w) in nouveau_connector_native_mode()
593 if (mode->hdisplay == high_w && mode->vdisplay < high_h) in nouveau_connector_native_mode()
596 if (mode->hdisplay == high_w && mode->vdisplay == high_h && in nouveau_connector_native_mode()
600 high_w = mode->hdisplay; in nouveau_connector_native_mode()
612 int hdisplay; member
646 while (mode->hdisplay) { in nouveau_connector_scaler_modes_add()
647 if (mode->hdisplay <= native->hdisplay && in nouveau_connector_scaler_modes_add()
649 m = drm_cvt_mode(dev, mode->hdisplay, mode->vdisplay, in nouveau_connector_scaler_modes_add()
815 (mode->hdisplay > nv_connector->native_mode->hdisplay || in nouveau_connector_mode_valid()
/drivers/gpu/drm/vmwgfx/
Dvmwgfx_scrn.c133 cmd->obj.size.width = mode->hdisplay; in vmw_sou_fifo_create()
145 cmd->obj.backingStore.pitch = mode->hdisplay * 4; in vmw_sou_fifo_create()
326 if (set->x + mode->hdisplay > fb->width || in vmw_sou_crtc_set_config()
334 if (mode->hdisplay != crtc->mode.hdisplay || in vmw_sou_crtc_set_config()
350 size_t size = mode->hdisplay * mode->vdisplay * 4; in vmw_sou_crtc_set_config()
/drivers/gpu/drm/tilcdc/
Dtilcdc_crtc.c279 hfp = mode->hsync_start - mode->hdisplay; in tilcdc_crtc_mode_set()
286 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); in tilcdc_crtc_mode_set()
299 reg = (((mode->hdisplay >> 4) - 1) << 4) | in tilcdc_crtc_mode_set()
304 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3; in tilcdc_crtc_mode_set()
426 if (mode->hdisplay > tilcdc_crtc_max_width(crtc)) in tilcdc_crtc_mode_valid()
430 if (mode->hdisplay & 0xf) in tilcdc_crtc_mode_valid()
437 bandwidth = mode->hdisplay * mode->vdisplay * drm_mode_vrefresh(mode); in tilcdc_crtc_mode_valid()
/drivers/gpu/drm/qxl/
Dqxl_display.c489 mode->hdisplay, mode->vdisplay, in qxl_crtc_mode_fixup()
490 adjusted_mode->hdisplay, in qxl_crtc_mode_fixup()
563 mode->hdisplay, mode->vdisplay, m->id); in qxl_crtc_mode_set()
566 mode->hdisplay, mode->vdisplay, in qxl_crtc_mode_set()
567 adjusted_mode->hdisplay, in qxl_crtc_mode_set()
572 width = mode->hdisplay; in qxl_crtc_mode_set()
604 mode->hdisplay, in qxl_crtc_mode_set()
613 crtc->mode.hdisplay, crtc->mode.vdisplay, in qxl_crtc_prepare()
705 head->width = mode->hdisplay; in qxl_write_monitors_config_for_encoder()
762 DRM_DEBUG("%s: %dx%d status=%d\n", mode->name, mode->hdisplay, in qxl_conn_mode_valid()

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