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Searched refs:hwirq (Results 1 – 25 of 48) sorted by relevance

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/drivers/irqchip/
Dirq-armada-370-xp.c68 irq_hw_number_t hwirq = irqd_to_hwirq(d); in armada_370_xp_irq_mask() local
70 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) in armada_370_xp_irq_mask()
71 writel(hwirq, main_int_base + in armada_370_xp_irq_mask()
74 writel(hwirq, per_cpu_int_base + in armada_370_xp_irq_mask()
80 irq_hw_number_t hwirq = irqd_to_hwirq(d); in armada_370_xp_irq_unmask() local
82 if (hwirq != ARMADA_370_XP_TIMER0_PER_CPU_IRQ) in armada_370_xp_irq_unmask()
83 writel(hwirq, main_int_base + in armada_370_xp_irq_unmask()
86 writel(hwirq, per_cpu_int_base + in armada_370_xp_irq_unmask()
98 irq_hw_number_t hwirq = irqd_to_hwirq(d); in armada_xp_set_affinity() local
119 reg = readl(main_int_base + ARMADA_370_XP_INT_SOURCE_CTL(hwirq)); in armada_xp_set_affinity()
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Dirq-vt8500.c88 void __iomem *stat_reg = base + VT8500_ICIS + (d->hwirq < 32 ? 0 : 4); in vt8500_irq_mask()
92 edge = readb(base + VT8500_ICDC + d->hwirq) & VT8500_EDGE; in vt8500_irq_mask()
96 status |= (1 << (d->hwirq & 0x1f)); in vt8500_irq_mask()
99 dctr = readb(base + VT8500_ICDC + d->hwirq); in vt8500_irq_mask()
101 writeb(dctr, base + VT8500_ICDC + d->hwirq); in vt8500_irq_mask()
111 dctr = readb(base + VT8500_ICDC + d->hwirq); in vt8500_irq_unmask()
113 writeb(dctr, base + VT8500_ICDC + d->hwirq); in vt8500_irq_unmask()
122 dctr = readb(base + VT8500_ICDC + d->hwirq); in vt8500_irq_set_type()
141 writeb(dctr, base + VT8500_ICDC + d->hwirq); in vt8500_irq_set_type()
Dirq-metag-ext.c132 irq_hw_number_t hw = data->hwirq; in meta_intc_startup_irq()
157 irq_hw_number_t hw = data->hwirq; in meta_intc_shutdown_irq()
178 irq_hw_number_t hw = data->hwirq; in meta_intc_ack_irq()
200 irq_hw_number_t hw = data->hwirq; in record_irq_is_masked()
216 irq_hw_number_t hw = data->hwirq; in record_irq_is_unmasked()
267 irq_hw_number_t hw = data->hwirq; in meta_intc_mask_irq()
290 irq_hw_number_t hw = data->hwirq; in meta_intc_unmask_irq()
313 irq_hw_number_t hw = data->hwirq; in meta_intc_mask_irq_nomask()
334 irq_hw_number_t hw = data->hwirq; in meta_intc_unmask_edge_irq_nomask()
375 irq_hw_number_t hw = data->hwirq; in meta_intc_unmask_level_irq_nomask()
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Dirq-sun4i.c141 u32 irq, hwirq; in sun4i_handle_irq() local
143 hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2; in sun4i_handle_irq()
144 while (hwirq != 0) { in sun4i_handle_irq()
145 irq = irq_find_mapping(sun4i_irq_domain, hwirq); in sun4i_handle_irq()
147 hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2; in sun4i_handle_irq()
Dirq-vic.c194 irq_hw_number_t hwirq) in vic_irqdomain_map() argument
199 if (!(v->valid_sources & (1 << hwirq))) in vic_irqdomain_map()
290 unsigned int irq = d->hwirq; in vic_ack_irq()
299 unsigned int irq = d->hwirq; in vic_mask_irq()
306 unsigned int irq = d->hwirq; in vic_unmask_irq()
328 unsigned int off = d->hwirq; in vic_set_wake()
Dirq-metag.c124 irq_hw_number_t hw = data->hwirq; in metag_internal_irq_ack()
141 irq_hw_number_t hw = data->hwirq; in metag_internal_irq_mask()
160 irq_hw_number_t hw = data->hwirq; in metag_internal_irq_unmask()
196 irq_hw_number_t hw = data->hwirq; in metag_internal_irq_set_affinity()
Dirq-versatile-fpga.c51 u32 mask = 1 << d->hwirq; in fpga_irq_mask()
59 u32 mask = 1 << d->hwirq; in fpga_irq_unmask()
116 irq_hw_number_t hwirq) in fpga_irqdomain_map() argument
121 if (!(f->valid & BIT(hwirq))) in fpga_irqdomain_map()
Dirq-bcm2835.c99 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]); in armctrl_mask_irq()
104 writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]); in armctrl_unmask_irq()
Dirq-s3c24xx.c225 if ((data->hwirq >= 4) && (data->hwirq <= 7)) { in s3c_irqext_type()
228 gpcon_offset = (data->hwirq) * 2; in s3c_irqext_type()
229 extint_offset = (data->hwirq) * 4; in s3c_irqext_type()
230 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) { in s3c_irqext_type()
233 gpcon_offset = (data->hwirq - 8) * 2; in s3c_irqext_type()
234 extint_offset = (data->hwirq - 8) * 4; in s3c_irqext_type()
235 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) { in s3c_irqext_type()
238 gpcon_offset = (data->hwirq - 8) * 2; in s3c_irqext_type()
239 extint_offset = (data->hwirq - 16) * 4; in s3c_irqext_type()
254 if ((data->hwirq >= 0) && (data->hwirq <= 3)) { in s3c_irqext0_type()
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Dirq-mxs.c60 icoll_base + HW_ICOLL_INTERRUPTn_CLR(d->hwirq)); in icoll_mask_irq()
66 icoll_base + HW_ICOLL_INTERRUPTn_SET(d->hwirq)); in icoll_unmask_irq()
Dspear-shirq.c254 int i, irq_base, hwirq = 0, irq_nr = 0; in shirq_init() local
283 hwirq); in shirq_init()
287 hwirq += shirq_blocks[i]->irq_nr; in shirq_init()
/drivers/gpio/
Dgpio-lynxpoint.c155 u32 hwirq = irqd_to_hwirq(d); in lp_irq_type() local
158 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1); in lp_irq_type()
160 if (hwirq >= lg->chip.ngpio) in lp_irq_type()
281 u32 hwirq = irqd_to_hwirq(d); in lp_irq_enable() local
282 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); in lp_irq_enable()
286 outl(inl(reg) | BIT(hwirq % 32), reg); in lp_irq_enable()
293 u32 hwirq = irqd_to_hwirq(d); in lp_irq_disable() local
294 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE); in lp_irq_disable()
298 outl(inl(reg) & ~BIT(hwirq % 32), reg); in lp_irq_disable()
351 unsigned hwirq; in lp_gpio_probe() local
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Dgpio-ts5500.c41 u8 hwirq; member
282 return priv->hwirq; in ts5500_gpio_to_irq()
293 if (priv->hwirq == 7) in ts5500_enable_irq()
295 else if (priv->hwirq == 6) in ts5500_enable_irq()
297 else if (priv->hwirq == 1) in ts5500_enable_irq()
311 if (priv->hwirq == 7) in ts5500_disable_irq()
313 else if (priv->hwirq == 6) in ts5500_disable_irq()
315 else if (priv->hwirq == 1) in ts5500_disable_irq()
318 dev_err(priv->gpio_chip.dev, "invalid hwirq %d\n", priv->hwirq); in ts5500_disable_irq()
344 priv->hwirq = res->start; in ts5500_dio_probe()
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Dgpio-rcar.c92 unsigned int hwirq, in gpio_rcar_config_interrupt_input_mode() argument
106 gpio_rcar_modify_bit(p, POSNEG, hwirq, !active_high_rising_edge); in gpio_rcar_config_interrupt_input_mode()
109 gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger); in gpio_rcar_config_interrupt_input_mode()
112 gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true); in gpio_rcar_config_interrupt_input_mode()
116 gpio_rcar_write(p, INTCLR, BIT(hwirq)); in gpio_rcar_config_interrupt_input_mode()
124 unsigned int hwirq = irqd_to_hwirq(d); in gpio_rcar_irq_set_type() local
126 dev_dbg(&p->pdev->dev, "sense irq = %d, type = %d\n", hwirq, type); in gpio_rcar_irq_set_type()
130 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true); in gpio_rcar_irq_set_type()
133 gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true); in gpio_rcar_irq_set_type()
136 gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false); in gpio_rcar_irq_set_type()
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Dgpio-stmpe.c138 int offset = d->hwirq; in stmpe_gpio_irq_set_type()
205 int offset = d->hwirq; in stmpe_gpio_irq_mask()
215 int offset = d->hwirq; in stmpe_gpio_irq_unmask()
275 irq_hw_number_t hwirq) in stmpe_gpio_irq_map() argument
282 irq_set_chip_data(hwirq, stmpe_gpio); in stmpe_gpio_irq_map()
283 irq_set_chip_and_handler(hwirq, &stmpe_gpio_irq_chip, in stmpe_gpio_irq_map()
285 irq_set_nested_thread(hwirq, 1); in stmpe_gpio_irq_map()
287 set_irq_flags(hwirq, IRQF_VALID); in stmpe_gpio_irq_map()
289 irq_set_noprobe(hwirq); in stmpe_gpio_irq_map()
Dgpio-mpc8xxx.c320 unsigned hwirq; in mpc8xxx_add_controller() local
348 hwirq = irq_of_parse_and_map(np, 0); in mpc8xxx_add_controller()
349 if (hwirq == NO_IRQ) in mpc8xxx_add_controller()
365 irq_set_handler_data(hwirq, mpc8xxx_gc); in mpc8xxx_add_controller()
366 irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade); in mpc8xxx_add_controller()
Dgpio-adnp.c346 unsigned int reg = data->hwirq >> adnp->reg_shift; in adnp_irq_mask()
347 unsigned int pos = data->hwirq & 7; in adnp_irq_mask()
355 unsigned int reg = data->hwirq >> adnp->reg_shift; in adnp_irq_unmask()
356 unsigned int pos = data->hwirq & 7; in adnp_irq_unmask()
364 unsigned int reg = data->hwirq >> adnp->reg_shift; in adnp_irq_set_type()
365 unsigned int pos = data->hwirq & 7; in adnp_irq_set_type()
421 irq_hw_number_t hwirq) in adnp_irq_map() argument
Dgpio-grgpio.c139 u32 mask = BIT(d->hwirq); in grgpio_irq_set_type()
182 int offset = d->hwirq; in grgpio_irq_mask()
190 int offset = d->hwirq; in grgpio_irq_unmask()
239 irq_hw_number_t hwirq) in grgpio_irq_map() argument
245 int offset = hwirq; in grgpio_irq_map()
Dgpio-pca953x.c380 chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ)); in pca953x_irq_mask()
387 chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ); in pca953x_irq_unmask()
422 int bank_nb = d->hwirq / BANK_SZ; in pca953x_irq_set_type()
423 u8 mask = 1 << (d->hwirq % BANK_SZ); in pca953x_irq_set_type()
522 irq_hw_number_t hwirq) in pca953x_gpio_irq_map() argument
Dgpio-tegra.c181 int gpio = d->hwirq; in tegra_gpio_irq_ack()
188 int gpio = d->hwirq; in tegra_gpio_irq_mask()
195 int gpio = d->hwirq; in tegra_gpio_irq_unmask()
202 int gpio = d->hwirq; in tegra_gpio_irq_set_type()
349 int gpio = d->hwirq; in tegra_gpio_irq_set_wake()
Dgpio-sodaville.c56 if (d->hwirq < 8) in sdv_gpio_pub_set_type()
65 reg &= ~BIT(4 * (d->hwirq % 8)); in sdv_gpio_pub_set_type()
69 reg |= BIT(4 * (d->hwirq % 8)); in sdv_gpio_pub_set_type()
/drivers/mfd/
Dlp8788-irq.c69 irqd->enabled[data->hwirq] = 1; in lp8788_irq_enable()
75 irqd->enabled[data->hwirq] = 0; in lp8788_irq_disable()
88 enum lp8788_int_id irq = data->hwirq; in lp8788_irq_bus_sync_unlock()
134 irq_hw_number_t hwirq) in lp8788_irq_map() argument
/drivers/pinctrl/
Dpinctrl-s3c64xx.c312 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; in s3c64xx_gpio_irq_set_mask()
338 unsigned char index = EINT_OFFS(bank->eint_offset) + irqd->hwirq; in s3c64xx_gpio_irq_ack()
363 shift = EINT_OFFS(bank->eint_offset) + irqd->hwirq; in s3c64xx_gpio_irq_set_type()
371 s3c64xx_irq_set_function(d, bank, irqd->hwirq); in s3c64xx_gpio_irq_set_type()
528 val |= 1 << ddata->eints[irqd->hwirq]; in s3c64xx_eint0_irq_set_mask()
530 val &= ~(1 << ddata->eints[irqd->hwirq]); in s3c64xx_eint0_irq_set_mask()
550 writel(1 << ddata->eints[irqd->hwirq], in s3c64xx_eint0_irq_ack()
575 shift = ddata->eints[irqd->hwirq]; in s3c64xx_eint0_irq_set_type()
587 s3c64xx_irq_set_function(d, bank, irqd->hwirq); in s3c64xx_eint0_irq_set_type()
Dpinctrl-exynos.c61 mask &= ~(1 << irqd->hwirq); in exynos_gpio_irq_unmask()
73 mask |= 1 << irqd->hwirq; in exynos_gpio_irq_mask()
83 writel(1 << irqd->hwirq, d->virt_base + reg_pend); in exynos_gpio_irq_ack()
92 unsigned int pin = irqd->hwirq; in exynos_gpio_irq_set_type()
269 mask &= ~(1 << irqd->hwirq); in exynos_wkup_irq_unmask()
281 mask |= 1 << irqd->hwirq; in exynos_wkup_irq_mask()
291 writel(1 << irqd->hwirq, d->virt_base + pend); in exynos_wkup_irq_ack()
299 unsigned int pin = irqd->hwirq; in exynos_wkup_irq_set_type()
363 unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq); in exynos_wkup_irq_set_wake()
/drivers/pcmcia/
Dm8xx_pcmcia.c214 int hwirq; member
746 mk_int_int_mask(s->hwirq) << 24); in m8xx_set_socket()
1013 unsigned int i, m, hwirq; in m8xx_probe() local
1025 hwirq = irq_map[pcmcia_schlvl].hwirq; in m8xx_probe()
1035 " with IRQ %u (%d). \n", pcmcia_schlvl, hwirq); in m8xx_probe()
1055 M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16)); in m8xx_probe()
1057 M8XX_PGCRX_CXOE | (mk_int_int_mask(hwirq) << 16)); in m8xx_probe()
1096 socket[i].hwirq = hwirq; in m8xx_probe()

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