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Searched refs:lane_count (Results 1 – 12 of 12) sorted by relevance

/drivers/video/exynos/
Dexynos_dp_core.c267 int lane, lane_count, pll_tries, retval; in exynos_dp_link_start() local
269 lane_count = dp->link_train.lane_count; in exynos_dp_link_start()
274 for (lane = 0; lane < lane_count; lane++) in exynos_dp_link_start()
279 exynos_dp_set_lane_count(dp, dp->link_train.lane_count); in exynos_dp_link_start()
283 buf[1] = dp->link_train.lane_count; in exynos_dp_link_start()
290 for (lane = 0; lane < lane_count; lane++) in exynos_dp_link_start()
316 for (lane = 0; lane < lane_count; lane++) in exynos_dp_link_start()
321 lane_count, buf); in exynos_dp_link_start()
334 static int exynos_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in exynos_dp_clock_recovery_ok() argument
339 for (lane = 0; lane < lane_count; lane++) { in exynos_dp_clock_recovery_ok()
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Dexynos_dp_core.h28 u8 lane_count; member
/drivers/gpu/drm/gma500/
Dcdv_intel_dp.c69 uint8_t lane_count; member
703 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
716 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
718 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup()
722 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
726 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
734 intel_dp->lane_count = max_lane_count; in cdv_intel_dp_mode_fixup()
739 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
796 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local
813 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
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Dmdfld_dsi_dpi.c470 int lane_count = dsi_config->lane_count; in mdfld_dsi_dpi_controller_init() local
485 val = lane_count; in mdfld_dsi_dpi_controller_init()
506 (8 * lane_count)) & DSI_HS_TX_TIMEOUT_MASK); in mdfld_dsi_dpi_controller_init()
523 dsi_config->lane_count, dsi_config->bpp); in mdfld_dsi_dpi_controller_init()
749 dsi_config->lane_count, in mdfld_mipi_set_video_timing()
773 int lane_count = dsi_config->lane_count; in mdfld_mipi_config() local
787 REG_WRITE(MIPI_DSI_FUNC_PRG_REG(pipe), 0x00000200 | lane_count); in mdfld_mipi_config()
Dmdfld_dsi_output.c435 config->lane_count = 4; in mdfld_dsi_get_default_config()
437 config->lane_count = 2; in mdfld_dsi_get_default_config()
Dmdfld_dsi_output.h260 int lane_count; member
/drivers/gpu/drm/
Ddrm_dp_helper.c246 int lane_count) in drm_dp_channel_eq_ok() argument
256 for (lane = 0; lane < lane_count; lane++) { in drm_dp_channel_eq_ok()
266 int lane_count) in drm_dp_clock_recovery_ok() argument
271 for (lane = 0; lane < lane_count; lane++) { in drm_dp_clock_recovery_ok()
/drivers/gpu/drm/i915/
Dintel_dp.c673 int lane_count, clock; in intel_dp_compute_config() local
712 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in intel_dp_compute_config()
715 lane_count); in intel_dp_compute_config()
743 intel_dp->lane_count = lane_count; in intel_dp_compute_config()
749 intel_dp->link_bw, intel_dp->lane_count, in intel_dp_compute_config()
754 intel_link_compute_m_n(bpp, lane_count, in intel_dp_compute_config()
765 intel_dp->link_configuration[1] = intel_dp->lane_count; in intel_dp_init_link_config()
837 switch (intel_dp->lane_count) { in intel_dp_mode_set()
1514 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_get_adjust_train()
1784 intel_dp->lane_count); in intel_dp_set_link_train()
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Dintel_ddi.c689 switch (intel_dp->lane_count) { in intel_ddi_mode_set()
702 intel_dp->lane_count); in intel_ddi_mode_set()
1033 switch (intel_dp->lane_count) { in intel_ddi_enable_transcoder_func()
1046 intel_dp->lane_count); in intel_ddi_enable_transcoder_func()
Dintel_drv.h409 uint8_t lane_count; member
/drivers/gpu/drm/radeon/
Datombios_dp.c296 int lane_count, in dp_get_adjust_train() argument
303 for (lane = 0; lane < lane_count; lane++) { in dp_get_adjust_train()
/drivers/edac/
Dppc4xx_edac.c444 const unsigned int lane_count = 16; in ppc4xx_edac_generate_lane_message() local
455 for (lanes = 0, lane = first_lane; lane < lane_count; lane++) { in ppc4xx_edac_generate_lane_message()