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Searched refs:mode_reg (Results 1 – 19 of 19) sorted by relevance

/drivers/clk/spear/
Dclk-vco-pll.c202 mode = (readl_relaxed(vco->mode_reg) >> PLL_MODE_SHIFT) & PLL_MODE_MASK; in clk_vco_recalc_rate()
244 val = readl_relaxed(vco->mode_reg); in clk_vco_set_rate()
247 writel_relaxed(val, vco->mode_reg); in clk_vco_set_rate()
277 unsigned long flags, void __iomem *mode_reg, void __iomem in clk_register_vco_pll() argument
288 if (!vco_name || !pll_name || !parent_name || !mode_reg || !cfg_reg || in clk_register_vco_pll()
307 vco->mode_reg = mode_reg; in clk_register_vco_pll()
319 parent_name, 0, mode_reg, PLL_ENABLE, 0, lock); in clk_register_vco_pll()
Dclk.h95 void __iomem *mode_reg; member
125 unsigned long flags, void __iomem *mode_reg, void __iomem
/drivers/atm/
DuPD98402.c104 unsigned char mode_reg; in set_loopback() local
106 mode_reg = GET(MDR) & ~(uPD98402_MDR_TPLP | uPD98402_MDR_ALP | in set_loopback()
112 mode_reg |= uPD98402_MDR_TPLP; in set_loopback()
115 mode_reg |= uPD98402_MDR_ALP; in set_loopback()
124 mode_reg |= uPD98402_MDR_RPLP; in set_loopback()
129 PUT(mode_reg,MDR); in set_loopback()
/drivers/gpu/drm/nouveau/dispnv04/
Ddfp.c95 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; in nv04_dfp_disable()
122 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; in nv04_dfp_update_fp_control()
137 fpc = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].fp_control; in nv04_dfp_update_fp_control()
206 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv04_dfp_prepare_sel_clk()
250 struct nv04_crtc_reg *crtcstate = nv04_display(dev)->mode_reg.crtc_reg; in nv04_dfp_prepare()
287 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_dfp_mode_set()
462 nv04_display(dev)->mode_reg.crtc_reg[head].fp_control = in nv04_dfp_commit()
553 nv04_display(dev)->mode_reg.sel_clk = NVReadRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK); in nv04_lvds_dpms()
554 nv04_display(dev)->mode_reg.sel_clk &= ~0xf0; in nv04_lvds_dpms()
556 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); in nv04_lvds_dpms()
Dcrtc.c59 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_digital_vibrance()
74 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_set_image_sharpening()
116 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv_crtc_calc_state_ext()
240 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_vga()
467 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv_crtc_mode_set_regs()
635 NVWriteRAMDAC(dev, 0, NV_PRAMDAC_SEL_CLK, nv04_display(dev)->mode_reg.sel_clk); in nv_crtc_mode_set()
645 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv_crtc_save()
707 nouveau_hw_load_state(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); in nv_crtc_commit()
746 rgbs = (struct rgb *)nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index].DAC; in nv_crtc_gamma_load()
753 nouveau_hw_load_state_palette(dev, nv_crtc->index, &nv04_display(dev)->mode_reg); in nv_crtc_gamma_load()
[all …]
Dtvnv04.c75 struct nv04_mode_state *state = &nv04_display(dev)->mode_reg; in nv04_tv_dpms()
103 struct nv04_crtc_reg *state = &nv04_display(dev)->mode_reg.crtc_reg[head]; in nv04_tv_bind()
142 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_tv_mode_set()
Dcursor.c42 struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index]; in nv04_cursor_set_offset()
Ddisp.h79 struct nv04_mode_state mode_reg; member
Dtvnv17.c416 uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[ in nv17_tv_prepare()
477 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head]; in nv17_tv_mode_set()
Dhw.h377 &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_HCUR_ADDR1_INDEX]; in nv_show_cursor()
Dtvmodesnv17.c548 struct nv04_crtc_reg *regs = &nv04_display(dev)->mode_reg.crtc_reg[head]; in nv17_ctv_update_rescaler()
/drivers/mfd/
Dmenelaus.c454 u8 mode_reg; member
486 ret = menelaus_write_reg(vtg->mode_reg, mode); in menelaus_set_voltage()
603 .mode_reg = MENELAUS_LDO_CTRL3,
632 .mode_reg = MENELAUS_LDO_CTRL4,
672 .mode_reg = MENELAUS_DCDC_CTRL2,
680 .mode_reg = MENELAUS_DCDC_CTRL3,
717 .mode_reg = MENELAUS_LDO_CTRL7,
747 .mode_reg = MENELAUS_LDO_CTRL6,
/drivers/net/ethernet/
Ddnet.c184 u32 mode_reg, ctl_reg; in dnet_handle_link_change() local
190 mode_reg = dnet_readw_mac(bp, DNET_INTERNAL_MODE_REG); in dnet_handle_link_change()
210 mode_reg |= DNET_INTERNAL_MODE_GBITEN; in dnet_handle_link_change()
214 mode_reg &= ~DNET_INTERNAL_MODE_GBITEN; in dnet_handle_link_change()
229 mode_reg |= in dnet_handle_link_change()
232 mode_reg &= in dnet_handle_link_change()
245 dnet_writew_mac(bp, DNET_INTERNAL_MODE_REG, mode_reg); in dnet_handle_link_change()
/drivers/mmc/host/
Datmel-mci.c210 u32 mode_reg; member
748 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE); in atmci_pdc_set_single_buf()
943 atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE); in atmci_prepare_data_pdc()
1148 atmci_writel(host, ATMCI_MR, host->mode_reg); in atmci_start_request()
1283 if (!host->mode_reg) { in atmci_set_ios()
1311 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1) in atmci_set_ios()
1321 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv); in atmci_set_ios()
1330 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF); in atmci_set_ios()
1341 atmci_writel(host, ATMCI_MR, host->mode_reg); in atmci_set_ios()
1362 if (host->mode_reg) { in atmci_set_ios()
[all …]
/drivers/regulator/
Dab8500.c78 u8 mode_reg; member
359 reg = info->mode_reg; in ab8500_regulator_set_mode()
457 info->mode_bank, info->mode_reg, &val); in ab8500_regulator_get_mode()
1150 .mode_reg = 0x54,
1171 .mode_reg = 0x54,
1683 .mode_reg = 0x83,
1704 .mode_reg = 0x83,
/drivers/tty/serial/
Dxilinx_uartps.c431 unsigned int ctrl_reg, mode_reg; in xuartps_set_termios() local
492 mode_reg = xuartps_readl(XUARTPS_MR_OFFSET); in xuartps_set_termios()
/drivers/media/i2c/
Dmsp3400-kthreads.c91 int mode_reg; member
238 msp_write_dem(client, 0x0083, data->mode_reg); in msp3400c_set_mode()
/drivers/scsi/
Dnsp32.c1453 unsigned char mode_reg; in nsp32_show_info() local
1470 mode_reg = nsp32_index_read1(base, CHIP_MODE); in nsp32_show_info()
1474 SPRINTF("Power Management: %s\n", (mode_reg & OPTF) ? "yes" : "no"); in nsp32_show_info()
1476 SPRINTF("OEM: %ld, %s\n", (mode_reg & (OEM0|OEM1)), nsp32_model[model]); in nsp32_show_info()
/drivers/video/
Dw100fb.c1412 writel(bm_mem->mode_reg, remapped_regs + mmBM_MEM_MODE_REG); in w100_setup_memory()