Home
last modified time | relevance | path

Searched refs:mpll (Results 1 – 7 of 7) sorted by relevance

/drivers/gpu/drm/radeon/
Dradeon_clocks.c67 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_legacy_get_memory_clock() local
73 fb_div *= mpll->reference_freq; in radeon_legacy_get_memory_clock()
107 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_read_clocks_OF() local
145 spll->reference_freq = mpll->reference_freq = p1pll->reference_freq; in radeon_read_clocks_OF()
146 spll->reference_div = mpll->reference_div = in radeon_read_clocks_OF()
182 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_get_clock_info() local
214 if (mpll->reference_div < 2) in radeon_get_clock_info()
215 mpll->reference_div = spll->reference_div; in radeon_get_clock_info()
229 mpll->reference_freq = 1432; in radeon_get_clock_info()
234 mpll->reference_freq = 2700; in radeon_get_clock_info()
[all …]
Dradeon_combios.c816 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_combios_get_clock_info() local
857 mpll->reference_freq = RBIOS16(pll_info + 0x26); in radeon_combios_get_clock_info()
858 mpll->reference_div = RBIOS16(pll_info + 0x28); in radeon_combios_get_clock_info()
859 mpll->pll_out_min = RBIOS32(pll_info + 0x2a); in radeon_combios_get_clock_info()
860 mpll->pll_out_max = RBIOS32(pll_info + 0x2e); in radeon_combios_get_clock_info()
863 mpll->pll_in_min = RBIOS32(pll_info + 0x5a); in radeon_combios_get_clock_info()
864 mpll->pll_in_max = RBIOS32(pll_info + 0x5e); in radeon_combios_get_clock_info()
867 mpll->pll_in_min = 40; in radeon_combios_get_clock_info()
868 mpll->pll_in_max = 500; in radeon_combios_get_clock_info()
Dradeon_atombios.c1130 struct radeon_pll *mpll = &rdev->clock.mpll; in radeon_atom_get_clock_info() local
1209 mpll->reference_freq = in radeon_atom_get_clock_info()
1212 mpll->reference_freq = in radeon_atom_get_clock_info()
1214 mpll->reference_div = 0; in radeon_atom_get_clock_info()
1216 mpll->pll_out_min = in radeon_atom_get_clock_info()
1218 mpll->pll_out_max = in radeon_atom_get_clock_info()
1222 if (mpll->pll_out_min == 0) { in radeon_atom_get_clock_info()
1224 mpll->pll_out_min = 64800; in radeon_atom_get_clock_info()
1226 mpll->pll_out_min = 20000; in radeon_atom_get_clock_info()
1229 mpll->pll_in_min = in radeon_atom_get_clock_info()
[all …]
Dradeon.h190 struct radeon_pll mpll; member
/drivers/gpu/drm/nouveau/core/subdev/clock/
Dnv04.c208 bool mpll = Preg == 0x4020; in setPLL_double_lowregs() local
211 uint32_t Pval = (oldPval & (mpll ? ~(0x77 << 16) : ~(7 << 16))) | in setPLL_double_lowregs()
226 if (mpll) { in setPLL_double_lowregs()
242 Pval |= mpll ? 1 << 12 : 1 << 8; in setPLL_double_lowregs()
246 if (mpll) { in setPLL_double_lowregs()
260 if (mpll) { in setPLL_double_lowregs()
269 if (mpll) { in setPLL_double_lowregs()
/drivers/clk/samsung/
Dclk-exynos4.c989 struct clk *apll, *mpll, *epll, *vpll; in exynos4_clk_init() local
1016 mpll = samsung_clk_register_pll45xx("fout_mpll", "fin_pll", in exynos4_clk_init()
1025 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll", in exynos4_clk_init()
1034 samsung_clk_add_lookup(mpll, fout_mpll); in exynos4_clk_init()
Dclk-exynos5250.c476 struct clk *apll, *mpll, *epll, *vpll, *bpll, *gpll, *cpll; in exynos5250_clk_init() local
495 mpll = samsung_clk_register_pll35xx("fout_mpll", "fin_pll", in exynos5250_clk_init()