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Searched refs:mw32 (Results 1 – 4 of 4) sorted by relevance

/drivers/scsi/mvsas/
Dmv_64xx.c54 mw32(MVS_PCS, tmp); in mvs_64xx_enable_xmt()
71 mw32(MVS_GBL_PORT_TYPE, 0); in mvs_64xx_phy_hacks()
114 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_stp_reset()
116 mw32(MVS_PHY_CTL, reg); in mvs_64xx_stp_reset()
147 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_64xx_clear_srs_irq()
154 mw32(MVS_INT_STAT_SRS_0, 1 << (reg_set % 32)); in mvs_64xx_clear_srs_irq()
166 mw32(MVS_GBL_CTL, 0); in mvs_64xx_chip_reset()
185 mw32(MVS_GBL_CTL, 0); in mvs_64xx_chip_reset()
227 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_phy_disable()
249 mw32(MVS_PHY_CTL, tmp); in mvs_64xx_phy_enable()
[all …]
Dmv_94xx.c267 mw32(MVS_PCS, tmp); in mvs_94xx_enable_xmt()
346 mw32(MVS_PHY_CTL, tmp); in mvs_94xx_init()
363 mw32(MVS_PHY_CTL, tmp); in mvs_94xx_init()
366 mw32(MVS_PHY_CTL, tmp); in mvs_94xx_init()
371 mw32(MVS_PORTS_IMP, 0xFF); in mvs_94xx_init()
374 mw32(MVS_PA_VSR_ADDR, CMD_CMWK_OOB_DET); in mvs_94xx_init()
375 mw32(MVS_PA_VSR_PORT, 0x00018080); in mvs_94xx_init()
377 mw32(MVS_PA_VSR_ADDR, VSR_PHY_MODE2); in mvs_94xx_init()
380 mw32(MVS_PA_VSR_PORT, 0x0084d4fe); in mvs_94xx_init()
383 mw32(MVS_PA_VSR_PORT, 0x0084fffe); in mvs_94xx_init()
[all …]
Dmv_chips.h31 #define mw32(reg, val) writel((val), regs + reg) macro
33 mw32(reg, val); \
47 mw32(MVS_CMD_ADDR, addr); in mvs_cr32()
54 mw32(MVS_CMD_ADDR, addr); in mvs_cw32()
55 mw32(MVS_CMD_DATA, val); in mvs_cw32()
69 mw32(MVS_P0_SER_CTLSTAT + port * 4, val); in mvs_write_phy_ctl()
71 mw32(MVS_P4_SER_CTLSTAT + (port - 4) * 4, val); in mvs_write_phy_ctl()
193 mw32(MVS_INT_STAT_SRS_0, tmp); in mvs_int_sata()
218 mw32(MVS_INT_STAT, stat); in mvs_int_full()
224 mw32(MVS_TX_PROD_IDX, tx); in mvs_start_delivery()
Dmv_94xx.h273 (((i) > 31) ? mw32(MVS_STP_REG_SET_1, tmp) : \
274 mw32(MVS_STP_REG_SET_0, tmp))