| /drivers/clk/ |
| D | clk-highbank.c | 106 unsigned long parent_rate) in clk_pll_recalc_rate() argument
113 return parent_rate; in clk_pll_recalc_rate()
117 vco_freq = parent_rate * (divf + 1); in clk_pll_recalc_rate()
147 unsigned long *parent_rate) in clk_pll_round_rate() argument
150 unsigned long ref_freq = *parent_rate; in clk_pll_round_rate()
158 unsigned long parent_rate) in clk_pll_set_rate() argument
164 clk_pll_calc(rate, parent_rate, &divq, &divf); in clk_pll_set_rate()
206 unsigned long parent_rate) in clk_cpu_periphclk_recalc_rate() argument
210 return parent_rate / div; in clk_cpu_periphclk_recalc_rate()
218 unsigned long parent_rate) in clk_cpu_a9bclk_recalc_rate() argument
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| D | clk-vt8500.c | 105 unsigned long parent_rate) in vt8500_dclk_recalc_rate() argument
118 return parent_rate / div; in vt8500_dclk_recalc_rate()
148 unsigned long parent_rate) in vt8500_dclk_set_rate() argument
157 divisor = parent_rate / rate; in vt8500_dclk_set_rate()
160 if (rate * divisor < parent_rate) in vt8500_dclk_set_rate()
331 static void vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate, in vt8500_find_pll_bits() argument
337 if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) { in vt8500_find_pll_bits()
343 if (rate <= parent_rate * 31) in vt8500_find_pll_bits()
349 *multiplier = rate / (parent_rate / *prediv); in vt8500_find_pll_bits()
350 tclk = (parent_rate / *prediv) * *multiplier; in vt8500_find_pll_bits()
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| D | clk-si5351.c | 270 unsigned long parent_rate) in si5351_clkin_recalc_rate() argument
277 rate = parent_rate; in si5351_clkin_recalc_rate()
278 if (parent_rate > 160000000) { in si5351_clkin_recalc_rate()
281 } else if (parent_rate > 80000000) { in si5351_clkin_recalc_rate()
284 } else if (parent_rate > 40000000) { in si5351_clkin_recalc_rate()
325 unsigned long parent_rate) in si5351_vxco_recalc_rate() argument
419 unsigned long parent_rate) in si5351_pll_recalc_rate() argument
431 return parent_rate; in si5351_pll_recalc_rate()
437 rate *= parent_rate; in si5351_pll_recalc_rate()
444 parent_rate, (unsigned long)rate); in si5351_pll_recalc_rate()
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| D | clk-divider.c | 102 unsigned long parent_rate) in clk_divider_recalc_rate() argument
115 return parent_rate; in clk_divider_recalc_rate()
118 return parent_rate / div; in clk_divider_recalc_rate()
152 unsigned long parent_rate, best = 0, now, maxdiv; in clk_divider_bestdiv() local
160 parent_rate = *best_parent_rate; in clk_divider_bestdiv()
161 bestdiv = DIV_ROUND_UP(parent_rate, rate); in clk_divider_bestdiv()
176 parent_rate = __clk_round_rate(__clk_get_parent(hw->clk), in clk_divider_bestdiv()
178 now = parent_rate / i; in clk_divider_bestdiv()
182 *best_parent_rate = parent_rate; in clk_divider_bestdiv()
204 unsigned long parent_rate) in clk_divider_set_rate() argument
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| D | clk-zynq.c | 38 unsigned long parent_rate) in zynq_pll_recalc_rate() argument
41 return parent_rate * CTRL_PLL_FDIV(ioread32(pll->pll_ctrl)); in zynq_pll_recalc_rate()
104 unsigned long parent_rate) in zynq_periph_recalc_rate() argument
107 return parent_rate / PERIPH_CLK_CTRL_DIV(ioread32(periph->clk_ctrl)); in zynq_periph_recalc_rate()
221 unsigned long parent_rate) in zynq_cpu_clk_recalc_rate() argument
224 return parent_rate / CPU_CLK_CTRL_DIV(ioread32(cpuclk->clk_ctrl)); in zynq_cpu_clk_recalc_rate()
248 unsigned long parent_rate) in zynq_cpu_subclk_recalc_rate() argument
259 rate = parent_rate; in zynq_cpu_subclk_recalc_rate()
262 rate = parent_rate / 2; in zynq_cpu_subclk_recalc_rate()
265 rate = parent_rate / (is_621 ? 3 : 2); in zynq_cpu_subclk_recalc_rate()
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| D | clk-axi-clkgen.c | 165 unsigned long rate, unsigned long parent_rate) in axi_clkgen_set_rate() argument
176 if (parent_rate == 0 || rate == 0) in axi_clkgen_set_rate()
179 axi_clkgen_calc_params(parent_rate, rate, &d, &m, &dout); in axi_clkgen_set_rate()
219 unsigned long *parent_rate) in axi_clkgen_round_rate() argument
223 axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout); in axi_clkgen_round_rate()
228 return *parent_rate / d * m / dout; in axi_clkgen_round_rate()
232 unsigned long parent_rate) in axi_clkgen_recalc_rate() argument
249 tmp = (unsigned long long)(parent_rate / d) * m; in axi_clkgen_recalc_rate()
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| D | clk-u300.c | 223 unsigned long parent_rate) in syscon_clk_recalc_rate() argument
240 return parent_rate; /* 26 MHz */ in syscon_clk_recalc_rate()
253 return parent_rate; /* 52 MHz */ in syscon_clk_recalc_rate()
278 return parent_rate; /* 208 MHz */ in syscon_clk_recalc_rate()
285 return parent_rate; in syscon_clk_recalc_rate()
308 unsigned long parent_rate) in syscon_clk_set_rate() argument
430 unsigned long parent_rate) in mclk_clk_recalc_rate() argument
488 return parent_rate; in mclk_clk_recalc_rate()
514 unsigned long parent_rate) in mclk_clk_set_rate() argument
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| D | clk-prima2.c | 105 unsigned long parent_rate) in pll_clk_recalc_rate() argument
107 unsigned long fin = parent_rate; in pll_clk_recalc_rate()
127 unsigned long *parent_rate) in pll_clk_round_rate() argument
143 fin = *parent_rate; in pll_clk_round_rate()
154 unsigned long parent_rate) in pll_clk_set_rate() argument
168 fin = parent_rate; in pll_clk_set_rate()
264 static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) in usb_pll_clk_recalc_rate() argument
267 return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ; in usb_pll_clk_recalc_rate()
332 unsigned long parent_rate) in dmn_clk_recalc_rate() argument
335 unsigned long fin = parent_rate; in dmn_clk_recalc_rate()
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| D | clk-fixed-factor.c | 29 unsigned long parent_rate) in clk_factor_recalc_rate() argument
34 rate = (unsigned long long int)parent_rate * fix->mult; in clk_factor_recalc_rate()
56 unsigned long parent_rate) in clk_factor_set_rate() argument
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| D | clk-composite.c | 47 unsigned long parent_rate) in clk_composite_recalc_rate() argument
55 return rate_ops->recalc_rate(rate_hw, parent_rate); in clk_composite_recalc_rate()
71 unsigned long parent_rate) in clk_composite_set_rate() argument
79 return rate_ops->set_rate(rate_hw, rate, parent_rate); in clk_composite_set_rate()
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| /drivers/clk/mxs/ |
| D | clk-frac.c | 41 unsigned long parent_rate) in clk_frac_recalc_rate() argument
49 return (parent_rate >> frac->width) * div; in clk_frac_recalc_rate()
56 unsigned long parent_rate = *prate; in clk_frac_round_rate() local
60 if (rate > parent_rate) in clk_frac_round_rate()
65 do_div(tmp, parent_rate); in clk_frac_round_rate()
71 return (parent_rate >> frac->width) * div; in clk_frac_round_rate()
75 unsigned long parent_rate) in clk_frac_set_rate() argument
82 if (rate > parent_rate) in clk_frac_set_rate()
87 do_div(tmp, parent_rate); in clk_frac_set_rate()
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| D | clk-ref.c | 55 unsigned long parent_rate) in clk_ref_recalc_rate() argument
58 u64 tmp = parent_rate; in clk_ref_recalc_rate()
70 unsigned long parent_rate = *prate; in clk_ref_round_rate() local
71 u64 tmp = parent_rate; in clk_ref_round_rate()
83 tmp = parent_rate; in clk_ref_round_rate()
91 unsigned long parent_rate) in clk_ref_set_rate() argument
95 u64 tmp = parent_rate; in clk_ref_set_rate()
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| D | clk-div.c | 43 unsigned long parent_rate) in clk_div_recalc_rate() argument
47 return div->ops->recalc_rate(&div->divider.hw, parent_rate); in clk_div_recalc_rate()
59 unsigned long parent_rate) in clk_div_set_rate() argument
64 ret = div->ops->set_rate(&div->divider.hw, rate, parent_rate); in clk_div_set_rate()
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| /drivers/clk/tegra/ |
| D | clk-pll.c | 302 unsigned long rate, unsigned long parent_rate) in _get_table_rate() argument
308 if (sel->input_rate == parent_rate && in _get_table_rate()
326 unsigned long rate, unsigned long parent_rate) in _calc_rate() argument
333 switch (parent_rate) { in _calc_rate()
350 cfreq = parent_rate/(parent_rate/1000000); in _calc_rate()
354 __func__, parent_rate); in _calc_rate()
363 cfg->m = parent_rate / cfreq; in _calc_rate()
470 unsigned long parent_rate) in clk_pll_set_rate() argument
487 if (_get_table_rate(hw, &cfg, rate, parent_rate) && in clk_pll_set_rate()
488 _calc_rate(hw, &cfg, rate, parent_rate)) in clk_pll_set_rate()
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| D | clk-divider.c | 34 unsigned long parent_rate) in get_div() argument
36 s64 divider_ux1 = parent_rate; in get_div()
68 unsigned long parent_rate) in clk_frac_div_recalc_rate() argument
73 u64 rate = parent_rate; in clk_frac_div_recalc_rate()
108 unsigned long parent_rate) in clk_frac_div_set_rate() argument
115 div = get_div(divider, rate, parent_rate); in clk_frac_div_set_rate()
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| D | clk-periph.c | 48 unsigned long parent_rate) in clk_periph_recalc_rate() argument
56 return div_ops->recalc_rate(div_hw, parent_rate); in clk_periph_recalc_rate()
72 unsigned long parent_rate) in clk_periph_set_rate() argument
80 return div_ops->set_rate(div_hw, rate, parent_rate); in clk_periph_set_rate()
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| /drivers/clk/sunxi/ |
| D | clk-sunxi.c | 82 static void sunxi_get_pll1_factors(u32 *freq, u32 parent_rate, in sunxi_get_pll1_factors() argument
135 static void sunxi_get_apb1_factors(u32 *freq, u32 parent_rate, in sunxi_get_apb1_factors() argument
140 if (parent_rate < *freq) in sunxi_get_apb1_factors()
141 *freq = parent_rate; in sunxi_get_apb1_factors()
143 parent_rate = (parent_rate + (*freq - 1)) / *freq; in sunxi_get_apb1_factors()
146 if (parent_rate > 32) in sunxi_get_apb1_factors()
149 if (parent_rate <= 4) in sunxi_get_apb1_factors()
151 else if (parent_rate <= 8) in sunxi_get_apb1_factors()
153 else if (parent_rate <= 16) in sunxi_get_apb1_factors()
158 calcm = (parent_rate >> calcp) - 1; in sunxi_get_apb1_factors()
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| D | clk-factors.c | 51 unsigned long parent_rate) in clk_factors_recalc_rate() argument
73 rate = (parent_rate * n * (k + 1) >> p) / (m + 1); in clk_factors_recalc_rate()
79 unsigned long *parent_rate) in clk_factors_round_rate() argument
82 factors->get_factors((u32 *)&rate, (u32)*parent_rate, in clk_factors_round_rate()
89 unsigned long parent_rate) in clk_factors_set_rate() argument
97 factors->get_factors((u32 *)&rate, (u32)parent_rate, &n, &k, &m, &p); in clk_factors_set_rate()
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| /drivers/clk/mvebu/ |
| D | clk-cpu.c | 40 unsigned long parent_rate) in clk_cpu_recalc_rate() argument
47 return parent_rate / div; in clk_cpu_recalc_rate()
51 unsigned long *parent_rate) in clk_cpu_round_rate() argument
56 div = *parent_rate / rate; in clk_cpu_round_rate()
62 return *parent_rate / div; in clk_cpu_round_rate()
66 unsigned long parent_rate) in clk_cpu_set_rate() argument
72 div = parent_rate / rate; in clk_cpu_set_rate()
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| /drivers/clk/spear/ |
| D | clk-frac-synth.c | 69 unsigned long parent_rate) in clk_frac_recalc_rate() argument
88 parent_rate = parent_rate / 10000; in clk_frac_recalc_rate()
90 parent_rate = (parent_rate << 14) / (2 * div); in clk_frac_recalc_rate()
91 return parent_rate * 10000; in clk_frac_recalc_rate()
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| D | clk.c | 17 unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt, in clk_round_rate_index() argument
24 rate = calc_rate(hw, parent_rate, *index); in clk_round_rate_index()
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| /drivers/clk/samsung/ |
| D | clk-pll.c | 35 unsigned long parent_rate) in samsung_pll35xx_recalc_rate() argument
39 u64 fvco = parent_rate; in samsung_pll35xx_recalc_rate()
111 unsigned long parent_rate) in samsung_pll36xx_recalc_rate() argument
116 u64 fvco = parent_rate; in samsung_pll36xx_recalc_rate()
191 unsigned long parent_rate) in samsung_pll45xx_recalc_rate() argument
195 u64 fvco = parent_rate; in samsung_pll45xx_recalc_rate()
276 unsigned long parent_rate) in samsung_pll46xx_recalc_rate() argument
280 u64 fvco = parent_rate; in samsung_pll46xx_recalc_rate()
361 unsigned long parent_rate) in samsung_pll2550x_recalc_rate() argument
365 u64 fvco = parent_rate; in samsung_pll2550x_recalc_rate()
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| /drivers/clk/socfpga/ |
| D | clk.c | 56 unsigned long parent_rate) in clk_pll_recalc_rate() argument
65 return parent_rate; in clk_pll_recalc_rate()
69 vco_freq = parent_rate * (divf + 1); in clk_pll_recalc_rate()
79 unsigned long parent_rate) in clk_periclk_recalc_rate() argument
89 return parent_rate / div; in clk_periclk_recalc_rate()
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| /drivers/video/ |
| D | sh_mobile_hdmi.c | 815 unsigned long *hdmi_rate, unsigned long *parent_rate) in sh_hdmi_rate_error() argument
826 rate_error = pdata->clk_optimize_parent(target, hdmi_rate, parent_rate); in sh_hdmi_rate_error()
828 *parent_rate = clk_get_rate(clk_get_parent(hdmi->hdmi_clk)); in sh_hdmi_rate_error()
838 mode->refresh, *parent_rate); in sh_hdmi_rate_error()
844 unsigned long *parent_rate) in sh_hdmi_read_edid() argument
946 rate_error = sh_hdmi_rate_error(hdmi, mode, hdmi_rate, parent_rate); in sh_hdmi_read_edid()
990 parent_rate); in sh_hdmi_read_edid()
1149 unsigned long parent_rate) in sh_hdmi_clk_configure() argument
1153 if (parent_rate && clk_get_parent(hdmi->hdmi_clk)) { in sh_hdmi_clk_configure()
1154 ret = clk_set_rate(clk_get_parent(hdmi->hdmi_clk), parent_rate); in sh_hdmi_clk_configure()
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| /drivers/clk/versatile/ |
| D | clk-vexpress-osc.c | 34 unsigned long parent_rate) in vexpress_osc_recalc_rate() argument
45 unsigned long *parent_rate) in vexpress_osc_round_rate() argument
59 unsigned long parent_rate) in vexpress_osc_set_rate() argument
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