Searched refs:pipe_bpp (Results 1 – 8 of 8) sorted by relevance
612 if (intel_crtc->config.pipe_bpp > 24) in intel_hdmi_mode_set()799 if (pipe_config->pipe_bpp > 8*3 && HAS_PCH_SPLIT(dev)) { in intel_hdmi_compute_config()801 pipe_config->pipe_bpp = 12*3; in intel_hdmi_compute_config()804 pipe_config->pipe_bpp = 8*3; in intel_hdmi_compute_config()
331 if (lvds_bpp != pipe_config->pipe_bpp) { in intel_lvds_compute_config()333 pipe_config->pipe_bpp, lvds_bpp); in intel_lvds_compute_config()334 pipe_config->pipe_bpp = lvds_bpp; in intel_lvds_compute_config()
934 switch (intel_crtc->config.pipe_bpp) { in intel_ddi_set_pipe_settings()970 switch (intel_crtc->config.pipe_bpp) { in intel_ddi_enable_transcoder_func()
217 int pipe_bpp; member
4006 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { in intel_crtc_compute_config()4007 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ in intel_crtc_compute_config()4008 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { in intel_crtc_compute_config()4011 pipe_config->pipe_bpp = 8*3; in intel_crtc_compute_config()5142 switch (intel_crtc->config.pipe_bpp) { in ironlake_set_pipeconf()5482 intel_crtc->config.pipe_bpp); in ironlake_fdi_set_m_n()5488 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock, in ironlake_fdi_set_m_n()7579 pipe_config->pipe_bpp = bpp; in pipe_config_set_bpp()7592 pipe_config->pipe_bpp = connector->display_info.bpc*3; in pipe_config_set_bpp()7655 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; in intel_modeset_pipe_config()[all …]
704 bpp = min_t(int, 8*3, pipe_config->pipe_bpp); in intel_dp_compute_config()745 pipe_config->pipe_bpp = bpp; in intel_dp_compute_config()
922 pipe_config->pipe_bpp = 8*3; in intel_tv_compute_config()
1052 pipe_config->pipe_bpp = 8*3; in intel_sdvo_compute_config()