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Searched refs:pll_prediv (Results 1 – 9 of 9) sorted by relevance

/drivers/media/usb/dvb-usb/
Ddib0700_devices.c1497 .io.pll_prediv = 1,
1852 .io.pll_prediv = 3,
1887 u32 pll_prediv; /* New loopdiv */ member
1893 u32 pll_prediv; member
1909 adc->pll_prediv = prediv; in dib8096p_get_best_sampling()
1949 adc->pll_prediv = prediv; in dib8096p_get_best_sampling()
1963 if (adc->pll_loopdiv == 0 && adc->pll_prediv == 0) in dib8096p_get_best_sampling()
1990 pll.pll_prediv = adc.pll_prediv; in dib8096p_agc_startup()
2179 .io.pll_prediv = 1,
2198 .io.pll_prediv = 1,
[all …]
Ddib0700_core.c366 u8 pll_src, u8 pll_range, u8 clock_gpio3, u16 pll_prediv, in dib0700_set_clock() argument
380 st->buf[2] = (pll_prediv >> 8) & 0xff; /* MSB */ in dib0700_set_clock()
381 st->buf[3] = pll_prediv & 0xff; /* LSB */ in dib0700_set_clock()
Dcxusb.c994 .pll_prediv = 1,
/drivers/media/dvb-frontends/
Ddib8000.c673 (pll->pll_prediv << 8) | (pll->pll_ratio << 0)); in dib8000_reset_pll()
704 (pll->pll_prediv)); in dib8000_reset_pll()
723 u8 loopdiv, prediv, oldprediv = state->cfg.pll->pll_prediv ; in dib8000_update_pll()
730 if ((pll == NULL) || (pll->pll_prediv == prediv && in dib8000_update_pll()
734 …ediv: old = %d new = %d ; loopdiv : old = %d new = %d)", prediv, pll->pll_prediv, loopdiv, pll->p… in dib8000_update_pll()
743 (pll->pll_prediv & 0x3f)); in dib8000_update_pll()
749 internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio; in dib8000_update_pll()
769 …rediv: %d->%d)", state->current_demod_bw / 1000, bw / 1000, oldprediv, state->cfg.pll->pll_prediv); in dib8000_update_pll()
771 if (state->cfg.pll->pll_prediv != oldprediv) { in dib8000_update_pll()
775 …or %d MHz Bandwidth (prediv: %d, ratio: %d)", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll-… in dib8000_update_pll()
[all …]
Ddibx000_common.h120 u8 pll_prediv; member
Ddib0090.h23 u8 pll_prediv:6; member
Ddib7000p.c445 …e, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio << 6) | (bw->pll_prediv)); in dib7000p_reset_pll()
459 …dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw-… in dib7000p_reset_pll()
492 if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) { in dib7000p_update_pll()
493 …rediv: old = %d new = %d ; loopdiv : old = %d new = %d)", prediv, bw->pll_prediv, loopdiv, bw->pl… in dib7000p_update_pll()
498 …dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f… in dib7000p_update_pll()
503 internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */ in dib7000p_update_pll()
Ddib0090.c549 … != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && (!cfg->in_s… in dib0090_reset_digital()
561 …<< 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv); in dib0090_reset_digital()
621 … != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv)) && !cfg->io.pl… in dib0090_fw_reset_digital()
632 …<< 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_prediv); in dib0090_fw_reset_digital()
Ddib7000m.c411 reg_910 |= (bw->pll_prediv << 5); in dib7000m_reset_pll()
427 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0)); in dib7000mc_reset_pll()