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Searched refs:pll_ratio (Results 1 – 6 of 6) sorted by relevance

/drivers/media/usb/dvb-usb/
Ddib0700_devices.c1520 u8 pll_ratio; in dib8090_compute_pll_parameters() local
1522 for (pll_ratio = 17; pll_ratio <= 20; pll_ratio++) { in dib8090_compute_pll_parameters()
1523 freq_adc = 12 * pll_ratio * (1 << 8) / 16; in dib8090_compute_pll_parameters()
1529 deb_info("PLL ratio=%i rest=%i\n", pll_ratio, rest); in dib8090_compute_pll_parameters()
1531 optimal_pll_ratio = pll_ratio; in dib8090_compute_pll_parameters()
1544 u8 pll_ratio, band = BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000); in dib8096_set_param_override() local
1574 pll_ratio = dib8090_compute_pll_parameters(fe); in dib8096_set_param_override()
1575 if (pll_ratio == 17) in dib8096_set_param_override()
1577 else if (pll_ratio == 18) in dib8096_set_param_override()
1579 else if (pll_ratio == 19) in dib8096_set_param_override()
[all …]
Dcxusb.c995 .pll_ratio = 20,
/drivers/media/dvb-frontends/
Ddib7000p.c445 …dib7000p_write_word(state, 1856, (!bw->pll_reset << 13) | (bw->pll_range << 12) | (bw->pll_ratio <… in dib7000p_reset_pll()
453 clk_cfg0 = (1 << 15) | ((bw->pll_ratio & 0x3f) << 9) | in dib7000p_reset_pll()
459 …dib7000p_write_word(state, 903, (bw->pll_prediv << 5) | (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw-… in dib7000p_reset_pll()
492 if ((bw != NULL) && (bw->pll_prediv != prediv || bw->pll_ratio != loopdiv)) { in dib7000p_update_pll()
493 …ld = %d new = %d ; loopdiv : old = %d new = %d)", prediv, bw->pll_prediv, loopdiv, bw->pll_ratio); in dib7000p_update_pll()
498 …dib7000p_write_word(state, 1856, reg_1856 | ((bw->pll_ratio & 0x3f) << 6) | (bw->pll_prediv & 0x3f… in dib7000p_update_pll()
503 internal = 1000 * (xtal / bw->pll_prediv) * bw->pll_ratio; /* new internal */ in dib7000p_update_pll()
Ddibx000_common.h121 u8 pll_ratio; member
Ddib7000m.c397 reg_910 = (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset; in dib7000m_reset_pll()
410 reg_907 |= (bw->pll_ratio & 0x3f) << 9; in dib7000m_reset_pll()
427 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0)); in dib7000mc_reset_pll()
Ddib8000.c673 (pll->pll_prediv << 8) | (pll->pll_ratio << 0)); in dib8000_reset_pll()
703 (pll->pll_range<<12) | (pll->pll_ratio<<6) | in dib8000_reset_pll()
731 pll->pll_ratio == loopdiv)) in dib8000_update_pll()
734 … = %d new = %d ; loopdiv : old = %d new = %d)", prediv, pll->pll_prediv, loopdiv, pll->pll_ratio); in dib8000_update_pll()
742 ((pll->pll_ratio & 0x3f) << 6) | in dib8000_update_pll()
749 internal = 1000 * (xtal/pll->pll_prediv) * pll->pll_ratio; in dib8000_update_pll()
775 …andwidth (prediv: %d, ratio: %d)", bw/1000, state->cfg.pll->pll_prediv, state->cfg.pll->pll_ratio); in dib8000_update_pll()
780 ratio = state->cfg.pll->pll_ratio; in dib8000_update_pll()