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Searched refs:ramfc (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/nouveau/core/engine/fifo/
Dnv84.c193 nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset)); in nv84_fifo_chan_ctor_dma()
194 nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset)); in nv84_fifo_chan_ctor_dma()
195 nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset)); in nv84_fifo_chan_ctor_dma()
196 nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset)); in nv84_fifo_chan_ctor_dma()
197 nv_wo32(base->ramfc, 0x3c, 0x003f6078); in nv84_fifo_chan_ctor_dma()
198 nv_wo32(base->ramfc, 0x44, 0x01003fff); in nv84_fifo_chan_ctor_dma()
199 nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); in nv84_fifo_chan_ctor_dma()
200 nv_wo32(base->ramfc, 0x4c, 0xffffffff); in nv84_fifo_chan_ctor_dma()
201 nv_wo32(base->ramfc, 0x60, 0x7fffffff); in nv84_fifo_chan_ctor_dma()
202 nv_wo32(base->ramfc, 0x78, 0x00000000); in nv84_fifo_chan_ctor_dma()
[all …]
Dnv50.c226 nv_wo32(base->ramfc, 0x08, lower_32_bits(args->offset)); in nv50_fifo_chan_ctor_dma()
227 nv_wo32(base->ramfc, 0x0c, upper_32_bits(args->offset)); in nv50_fifo_chan_ctor_dma()
228 nv_wo32(base->ramfc, 0x10, lower_32_bits(args->offset)); in nv50_fifo_chan_ctor_dma()
229 nv_wo32(base->ramfc, 0x14, upper_32_bits(args->offset)); in nv50_fifo_chan_ctor_dma()
230 nv_wo32(base->ramfc, 0x3c, 0x003f6078); in nv50_fifo_chan_ctor_dma()
231 nv_wo32(base->ramfc, 0x44, 0x01003fff); in nv50_fifo_chan_ctor_dma()
232 nv_wo32(base->ramfc, 0x48, chan->base.pushgpu->node->offset >> 4); in nv50_fifo_chan_ctor_dma()
233 nv_wo32(base->ramfc, 0x4c, 0xffffffff); in nv50_fifo_chan_ctor_dma()
234 nv_wo32(base->ramfc, 0x60, 0x7fffffff); in nv50_fifo_chan_ctor_dma()
235 nv_wo32(base->ramfc, 0x78, 0x00000000); in nv50_fifo_chan_ctor_dma()
[all …]
Dnv40.c136 nv_wo32(priv->ramfc, chan->ramfc + ctx, nv_engctx(engctx)->addr); in nv40_fifo_context_attach()
172 nv_wo32(priv->ramfc, chan->ramfc + ctx, 0x00000000); in nv40_fifo_context_detach()
207 chan->ramfc = chan->base.chid * 128; in nv40_fifo_chan_ctor()
209 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); in nv40_fifo_chan_ctor()
210 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset); in nv40_fifo_chan_ctor()
211 nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); in nv40_fifo_chan_ctor()
212 nv_wo32(priv->ramfc, chan->ramfc + 0x18, 0x30000000 | in nv40_fifo_chan_ctor()
219 nv_wo32(priv->ramfc, chan->ramfc + 0x3c, 0x0001ffff); in nv40_fifo_chan_ctor()
276 nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); in nv40_fifo_ctor()
324 priv->ramfc->addr) >> 16) | in nv40_fifo_init()
Dnv10.c82 chan->ramfc = chan->base.chid * 32; in nv10_fifo_chan_ctor()
84 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); in nv10_fifo_chan_ctor()
85 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset); in nv10_fifo_chan_ctor()
86 nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); in nv10_fifo_chan_ctor()
87 nv_wo32(priv->ramfc, chan->ramfc + 0x14, in nv10_fifo_chan_ctor()
150 nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); in nv10_fifo_ctor()
Dnv17.c89 chan->ramfc = chan->base.chid * 64; in nv17_fifo_chan_ctor()
91 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); in nv17_fifo_chan_ctor()
92 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset); in nv17_fifo_chan_ctor()
93 nv_wo32(priv->ramfc, chan->ramfc + 0x0c, chan->base.pushgpu->addr >> 4); in nv17_fifo_chan_ctor()
94 nv_wo32(priv->ramfc, chan->ramfc + 0x14, in nv17_fifo_chan_ctor()
157 nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); in nv17_fifo_ctor()
186 nv_wr32(priv, NV03_PFIFO_RAMFC, priv->ramfc->addr >> 8 | 0x00010000); in nv17_fifo_init()
Dnv04.c140 chan->ramfc = chan->base.chid * 32; in nv04_fifo_chan_ctor()
142 nv_wo32(priv->ramfc, chan->ramfc + 0x00, args->offset); in nv04_fifo_chan_ctor()
143 nv_wo32(priv->ramfc, chan->ramfc + 0x04, args->offset); in nv04_fifo_chan_ctor()
144 nv_wo32(priv->ramfc, chan->ramfc + 0x08, chan->base.pushgpu->addr >> 4); in nv04_fifo_chan_ctor()
145 nv_wo32(priv->ramfc, chan->ramfc + 0x10, in nv04_fifo_chan_ctor()
163 nv_wo32(priv->ramfc, chan->ramfc + c->ctxp, 0x00000000); in nv04_fifo_chan_dtor()
193 struct nouveau_gpuobj *fctx = priv->ramfc; in nv04_fifo_chan_fini()
196 u32 data = chan->ramfc; in nv04_fifo_chan_fini()
583 nouveau_gpuobj_ref(imem->ramfc, &priv->ramfc); in nv04_fifo_ctor()
599 nouveau_gpuobj_ref(NULL, &priv->ramfc); in nv04_fifo_dtor()
[all …]
Dnv04.h148 struct nouveau_gpuobj *ramfc; member
158 u32 ramfc; member
Dnv50.h12 struct nouveau_gpuobj *ramfc; member
/drivers/gpu/drm/nouveau/core/subdev/instmem/
Dnv04.c140 NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc); in nv04_instmem_ctor()
157 nouveau_gpuobj_ref(NULL, &priv->ramfc); in nv04_instmem_dtor()
Dnv04.h19 struct nouveau_gpuobj *ramfc; member
Dnv40.c108 NVOBJ_FLAG_ZERO_ALLOC, &priv->ramfc); in nv40_instmem_ctor()