/drivers/pci/pcie/aer/ |
D | aerdrv.c | 127 u32 reg32; in aer_enable_rootport() local 139 pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, ®32); in aer_enable_rootport() 140 pci_write_config_dword(pdev, aer_pos + PCI_ERR_ROOT_STATUS, reg32); in aer_enable_rootport() 141 pci_read_config_dword(pdev, aer_pos + PCI_ERR_COR_STATUS, ®32); in aer_enable_rootport() 142 pci_write_config_dword(pdev, aer_pos + PCI_ERR_COR_STATUS, reg32); in aer_enable_rootport() 143 pci_read_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, ®32); in aer_enable_rootport() 144 pci_write_config_dword(pdev, aer_pos + PCI_ERR_UNCOR_STATUS, reg32); in aer_enable_rootport() 153 pci_read_config_dword(pdev, aer_pos + PCI_ERR_ROOT_COMMAND, ®32); in aer_enable_rootport() 154 reg32 |= ROOT_PORT_INTR_ON_MESG_MASK; in aer_enable_rootport() 155 pci_write_config_dword(pdev, aer_pos + PCI_ERR_ROOT_COMMAND, reg32); in aer_enable_rootport() [all …]
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D | ecrc.c | 52 u32 reg32; in enable_ecrc_checking() local 61 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32); in enable_ecrc_checking() 62 if (reg32 & PCI_ERR_CAP_ECRC_GENC) in enable_ecrc_checking() 63 reg32 |= PCI_ERR_CAP_ECRC_GENE; in enable_ecrc_checking() 64 if (reg32 & PCI_ERR_CAP_ECRC_CHKC) in enable_ecrc_checking() 65 reg32 |= PCI_ERR_CAP_ECRC_CHKE; in enable_ecrc_checking() 66 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32); in enable_ecrc_checking() 80 u32 reg32; in disable_ecrc_checking() local 89 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32); in disable_ecrc_checking() 90 reg32 &= ~(PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE); in disable_ecrc_checking() [all …]
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/drivers/pci/hotplug/ |
D | pcihp_slot.c | 99 u32 reg32; in program_hpp_type2() local 125 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32); in program_hpp_type2() 126 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or; in program_hpp_type2() 127 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32); in program_hpp_type2() 130 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32); in program_hpp_type2() 131 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or; in program_hpp_type2() 132 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32); in program_hpp_type2() 135 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32); in program_hpp_type2() 136 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or; in program_hpp_type2() 137 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32); in program_hpp_type2() [all …]
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D | acpiphp_glue.c | 157 u32 reg32; in device_is_managed_by_native_pciehp() local 162 if (pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32)) in device_is_managed_by_native_pciehp() 164 if (!(reg32 & PCI_EXP_SLTCAP_HPC)) in device_is_managed_by_native_pciehp()
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/drivers/pci/pcie/ |
D | aspm.c | 156 u32 reg32; in pcie_clkpm_cap_init() local 163 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32); in pcie_clkpm_cap_init() 164 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) { in pcie_clkpm_cap_init() 295 u32 reg32; in pcie_get_aspm_reg() local 297 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); in pcie_get_aspm_reg() 298 info->support = (reg32 & PCI_EXP_LNKCAP_ASPMS) >> 10; in pcie_get_aspm_reg() 299 info->latency_encoding_l0s = (reg32 & PCI_EXP_LNKCAP_L0SEL) >> 12; in pcie_get_aspm_reg() 300 info->latency_encoding_l1 = (reg32 & PCI_EXP_LNKCAP_L1EL) >> 15; in pcie_get_aspm_reg() 407 u32 reg32, encoding; in pcie_aspm_cap_init() local 415 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32); in pcie_aspm_cap_init() [all …]
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D | portdrv_core.c | 80 u32 reg32; in pcie_port_enable_msix() local 149 pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, ®32); in pcie_port_enable_msix() 150 entry = reg32 >> 27; in pcie_port_enable_msix() 256 u32 reg32; in get_port_device_capability() local 276 pcie_capability_read_dword(dev, PCI_EXP_SLTCAP, ®32); in get_port_device_capability() 277 if (reg32 & PCI_EXP_SLTCAP_HPC) { in get_port_device_capability()
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/drivers/ipack/carriers/ |
D | tpci200.c | 518 u32 reg32; in tpci200_pci_probe() local 552 reg32 = ioread32(tpci200->info->cfg_regs + LAS1_DESC); in tpci200_pci_probe() 553 reg32 |= 1 << LAS_BIT_BIGENDIAN; in tpci200_pci_probe() 554 iowrite32(reg32, tpci200->info->cfg_regs + LAS1_DESC); in tpci200_pci_probe() 556 reg32 = ioread32(tpci200->info->cfg_regs + LAS2_DESC); in tpci200_pci_probe() 557 reg32 |= 1 << LAS_BIT_BIGENDIAN; in tpci200_pci_probe() 558 iowrite32(reg32, tpci200->info->cfg_regs + LAS2_DESC); in tpci200_pci_probe()
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/drivers/net/wireless/ath/ath9k/ |
D | ar9002_phy.c | 69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0; in ar9002_hw_set_channel() local 76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL); in ar9002_hw_set_channel() 77 reg32 &= 0xc0000000; in ar9002_hw_set_channel() 148 reg32 = reg32 | in ar9002_hw_set_channel() 152 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9002_hw_set_channel()
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D | ar9003_phy.c | 71 u32 freq, chan_frac, div, channelSel = 0, reg32 = 0; in ar9003_hw_set_channel() local 140 reg32 = (bMode << 29); in ar9003_hw_set_channel() 141 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ar9003_hw_set_channel() 148 reg32 = (channelSel << 2) | (fracMode << 30) | in ar9003_hw_set_channel() 150 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel() 154 reg32 = (channelSel << 2) | (fracMode << 30) | in ar9003_hw_set_channel() 156 REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32); in ar9003_hw_set_channel()
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D | ar5008_phy.c | 80 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32, in ar5008_hw_phy_modify_rx_buffer() argument 87 tmp32 = ath9k_hw_reverse_bits(reg32, numBits); in ar5008_hw_phy_modify_rx_buffer() 180 u32 reg32 = 0; in ar5008_hw_set_channel() local 235 reg32 = in ar5008_hw_set_channel() 239 REG_WRITE(ah, AR_PHY(0x37), reg32); in ar5008_hw_set_channel()
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D | eeprom_4k.c | 364 u32 reg32, regOffset, regChainOffset; in ath9k_hw_set_4k_power_cal_table() local 428 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_4k_power_cal_table() 429 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_4k_power_cal_table() 434 reg32); in ath9k_hw_set_4k_power_cal_table()
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D | eeprom_def.c | 840 u32 reg32, regOffset, regChainOffset; in ath9k_hw_set_def_power_cal_table() local 958 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_def_power_cal_table() 959 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_def_power_cal_table() 964 reg32); in ath9k_hw_set_def_power_cal_table()
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D | eeprom_9287.c | 420 u32 reg32, regOffset, regChainOffset, regval; in ath9k_hw_set_ar9287_power_cal_table() local 536 reg32 = get_unaligned_le32(&pdadcValues[4 * j]); in ath9k_hw_set_ar9287_power_cal_table() 538 REG_WRITE(ah, regOffset, reg32); in ath9k_hw_set_ar9287_power_cal_table()
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/drivers/net/wireless/rtl818x/rtl8187/ |
D | dev.c | 1522 u32 reg32; in rtl8187_probe() local 1523 reg32 = rtl818x_ioread32(priv, &priv->map->TX_CONF); in rtl8187_probe() 1524 reg32 &= RTL818X_TX_CONF_HWVER_MASK; in rtl8187_probe() 1525 switch (reg32) { in rtl8187_probe()
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/drivers/pci/ |
D | probe.c | 959 u32 reg32; in set_pcie_hotplug_bridge() local 961 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); in set_pcie_hotplug_bridge() 962 if (reg32 & PCI_EXP_SLTCAP_HPC) in set_pcie_hotplug_bridge()
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/drivers/net/ethernet/broadcom/ |
D | tg3.c | 2512 u32 reg32, phy9_orig; in tg3_phy_reset_5703_4_5() local 2526 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) in tg3_phy_reset_5703_4_5() 2529 reg32 |= 0x3000; in tg3_phy_reset_5703_4_5() 2530 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5() 2568 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) { in tg3_phy_reset_5703_4_5() 2569 reg32 &= ~0x3000; in tg3_phy_reset_5703_4_5() 2570 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32); in tg3_phy_reset_5703_4_5()
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