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Searched refs:rxqaddr (Results 1 – 2 of 2) sorted by relevance

/drivers/net/ethernet/marvell/
Dsky2.c152 static const unsigned rxqaddr[] = { Q_R1, Q_R2 }; variable
1286 Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_checksum()
1322 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_rss()
1325 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), in rx_set_rss()
1342 unsigned rxq = rxqaddr[sky2->port]; in sky2_rx_stop()
1536 unsigned rxq = rxqaddr[sky2->port]; in sky2_rx_start()
1699 sky2_ramset(hw, rxqaddr[port], 0, rxspace); in sky2_hw_up()
2450 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD); in sky2_change_mtu()
2681 sky2_rx_update(netdev_priv(dev), rxqaddr[port]); in sky2_rx_done()
2708 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR), in sky2_rx_checksum()
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Dskge.c120 static const int rxqaddr[] = { Q_R1, Q_R2 }; variable
2591 skge_ramset(hw, rxqaddr[port], ram_addr, chunk); in skge_up()
2592 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean); in skge_up()
2600 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F); in skge_up()
2630 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP); in skge_rx_stop()
2633 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET); in skge_rx_stop()
3165 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F); in skge_poll()
3187 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START); in skge_poll()