1 /**************************************************************************
2 * Copyright (c) 2007-2011, Intel Corporation.
3 * All Rights Reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 *
18 **************************************************************************/
19
20 #ifndef _PSB_DRV_H_
21 #define _PSB_DRV_H_
22
23 #include <linux/kref.h>
24
25 #include <drm/drmP.h>
26 #include <drm/drm_global.h>
27 #include <drm/gma_drm.h>
28 #include "psb_reg.h"
29 #include "psb_intel_drv.h"
30 #include "intel_bios.h"
31 #include "gtt.h"
32 #include "power.h"
33 #include "opregion.h"
34 #include "oaktrail.h"
35
36 /* Append new drm mode definition here, align with libdrm definition */
37 #define DRM_MODE_SCALE_NO_SCALE 2
38
39 enum {
40 CHIP_PSB_8108 = 0, /* Poulsbo */
41 CHIP_PSB_8109 = 1, /* Poulsbo */
42 CHIP_MRST_4100 = 2, /* Moorestown/Oaktrail */
43 CHIP_MFLD_0130 = 3, /* Medfield */
44 };
45
46 #define IS_PSB(dev) (((dev)->pci_device & 0xfffe) == 0x8108)
47 #define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
48 #define IS_MFLD(dev) (((dev)->pci_device & 0xfff8) == 0x0130)
49
50 /*
51 * Driver definitions
52 */
53
54 #define DRIVER_NAME "gma500"
55 #define DRIVER_DESC "DRM driver for the Intel GMA500"
56
57 #define PSB_DRM_DRIVER_DATE "2011-06-06"
58 #define PSB_DRM_DRIVER_MAJOR 1
59 #define PSB_DRM_DRIVER_MINOR 0
60 #define PSB_DRM_DRIVER_PATCHLEVEL 0
61
62 /*
63 * Hardware offsets
64 */
65 #define PSB_VDC_OFFSET 0x00000000
66 #define PSB_VDC_SIZE 0x000080000
67 #define MRST_MMIO_SIZE 0x0000C0000
68 #define MDFLD_MMIO_SIZE 0x000100000
69 #define PSB_SGX_SIZE 0x8000
70 #define PSB_SGX_OFFSET 0x00040000
71 #define MRST_SGX_OFFSET 0x00080000
72 /*
73 * PCI resource identifiers
74 */
75 #define PSB_MMIO_RESOURCE 0
76 #define PSB_GATT_RESOURCE 2
77 #define PSB_GTT_RESOURCE 3
78 /*
79 * PCI configuration
80 */
81 #define PSB_GMCH_CTRL 0x52
82 #define PSB_BSM 0x5C
83 #define _PSB_GMCH_ENABLED 0x4
84 #define PSB_PGETBL_CTL 0x2020
85 #define _PSB_PGETBL_ENABLED 0x00000001
86 #define PSB_SGX_2D_SLAVE_PORT 0x4000
87
88 /* To get rid of */
89 #define PSB_TT_PRIV0_LIMIT (256*1024*1024)
90 #define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
91
92 /*
93 * SGX side MMU definitions (these can probably go)
94 */
95
96 /*
97 * Flags for external memory type field.
98 */
99 #define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
100 #define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
101 #define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
102 /*
103 * PTE's and PDE's
104 */
105 #define PSB_PDE_MASK 0x003FFFFF
106 #define PSB_PDE_SHIFT 22
107 #define PSB_PTE_SHIFT 12
108 /*
109 * Cache control
110 */
111 #define PSB_PTE_VALID 0x0001 /* PTE / PDE valid */
112 #define PSB_PTE_WO 0x0002 /* Write only */
113 #define PSB_PTE_RO 0x0004 /* Read only */
114 #define PSB_PTE_CACHED 0x0008 /* CPU cache coherent */
115
116 /*
117 * VDC registers and bits
118 */
119 #define PSB_MSVDX_CLOCKGATING 0x2064
120 #define PSB_TOPAZ_CLOCKGATING 0x2068
121 #define PSB_HWSTAM 0x2098
122 #define PSB_INSTPM 0x20C0
123 #define PSB_INT_IDENTITY_R 0x20A4
124 #define _PSB_IRQ_ASLE (1<<0)
125 #define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
126 #define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
127 #define _PSB_DPST_PIPEB_FLAG (1<<4)
128 #define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
129 #define _PSB_VSYNC_PIPEB_FLAG (1<<5)
130 #define _PSB_DPST_PIPEA_FLAG (1<<6)
131 #define _PSB_PIPEA_EVENT_FLAG (1<<6)
132 #define _PSB_VSYNC_PIPEA_FLAG (1<<7)
133 #define _MDFLD_MIPIA_FLAG (1<<16)
134 #define _MDFLD_MIPIC_FLAG (1<<17)
135 #define _PSB_IRQ_DISP_HOTSYNC (1<<17)
136 #define _PSB_IRQ_SGX_FLAG (1<<18)
137 #define _PSB_IRQ_MSVDX_FLAG (1<<19)
138 #define _LNC_IRQ_TOPAZ_FLAG (1<<20)
139
140 #define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
141 _PSB_VSYNC_PIPEB_FLAG)
142
143 /* This flag includes all the display IRQ bits excepts the vblank irqs. */
144 #define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
145 _MDFLD_PIPEB_EVENT_FLAG | \
146 _PSB_PIPEA_EVENT_FLAG | \
147 _PSB_VSYNC_PIPEA_FLAG | \
148 _MDFLD_MIPIA_FLAG | \
149 _MDFLD_MIPIC_FLAG)
150 #define PSB_INT_IDENTITY_R 0x20A4
151 #define PSB_INT_MASK_R 0x20A8
152 #define PSB_INT_ENABLE_R 0x20A0
153
154 #define _PSB_MMU_ER_MASK 0x0001FF00
155 #define _PSB_MMU_ER_HOST (1 << 16)
156 #define GPIOA 0x5010
157 #define GPIOB 0x5014
158 #define GPIOC 0x5018
159 #define GPIOD 0x501c
160 #define GPIOE 0x5020
161 #define GPIOF 0x5024
162 #define GPIOG 0x5028
163 #define GPIOH 0x502c
164 #define GPIO_CLOCK_DIR_MASK (1 << 0)
165 #define GPIO_CLOCK_DIR_IN (0 << 1)
166 #define GPIO_CLOCK_DIR_OUT (1 << 1)
167 #define GPIO_CLOCK_VAL_MASK (1 << 2)
168 #define GPIO_CLOCK_VAL_OUT (1 << 3)
169 #define GPIO_CLOCK_VAL_IN (1 << 4)
170 #define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
171 #define GPIO_DATA_DIR_MASK (1 << 8)
172 #define GPIO_DATA_DIR_IN (0 << 9)
173 #define GPIO_DATA_DIR_OUT (1 << 9)
174 #define GPIO_DATA_VAL_MASK (1 << 10)
175 #define GPIO_DATA_VAL_OUT (1 << 11)
176 #define GPIO_DATA_VAL_IN (1 << 12)
177 #define GPIO_DATA_PULLUP_DISABLE (1 << 13)
178
179 #define VCLK_DIVISOR_VGA0 0x6000
180 #define VCLK_DIVISOR_VGA1 0x6004
181 #define VCLK_POST_DIV 0x6010
182
183 #define PSB_COMM_2D (PSB_ENGINE_2D << 4)
184 #define PSB_COMM_3D (PSB_ENGINE_3D << 4)
185 #define PSB_COMM_TA (PSB_ENGINE_TA << 4)
186 #define PSB_COMM_HP (PSB_ENGINE_HP << 4)
187 #define PSB_COMM_USER_IRQ (1024 >> 2)
188 #define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
189 #define PSB_COMM_FW (2048 >> 2)
190
191 #define PSB_UIRQ_VISTEST 1
192 #define PSB_UIRQ_OOM_REPLY 2
193 #define PSB_UIRQ_FIRE_TA_REPLY 3
194 #define PSB_UIRQ_FIRE_RASTER_REPLY 4
195
196 #define PSB_2D_SIZE (256*1024*1024)
197 #define PSB_MAX_RELOC_PAGES 1024
198
199 #define PSB_LOW_REG_OFFS 0x0204
200 #define PSB_HIGH_REG_OFFS 0x0600
201
202 #define PSB_NUM_VBLANKS 2
203
204
205 #define PSB_2D_SIZE (256*1024*1024)
206 #define PSB_MAX_RELOC_PAGES 1024
207
208 #define PSB_LOW_REG_OFFS 0x0204
209 #define PSB_HIGH_REG_OFFS 0x0600
210
211 #define PSB_NUM_VBLANKS 2
212 #define PSB_WATCHDOG_DELAY (DRM_HZ * 2)
213 #define PSB_LID_DELAY (DRM_HZ / 10)
214
215 #define MDFLD_PNW_B0 0x04
216 #define MDFLD_PNW_C0 0x08
217
218 #define MDFLD_DSR_2D_3D_0 (1 << 0)
219 #define MDFLD_DSR_2D_3D_2 (1 << 1)
220 #define MDFLD_DSR_CURSOR_0 (1 << 2)
221 #define MDFLD_DSR_CURSOR_2 (1 << 3)
222 #define MDFLD_DSR_OVERLAY_0 (1 << 4)
223 #define MDFLD_DSR_OVERLAY_2 (1 << 5)
224 #define MDFLD_DSR_MIPI_CONTROL (1 << 6)
225 #define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
226 #define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
227 #define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
228
229 #define MDFLD_DSR_RR 45
230 #define MDFLD_DPU_ENABLE (1 << 31)
231 #define MDFLD_DSR_FULLSCREEN (1 << 30)
232 #define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
233
234 #define PSB_PWR_STATE_ON 1
235 #define PSB_PWR_STATE_OFF 2
236
237 #define PSB_PMPOLICY_NOPM 0
238 #define PSB_PMPOLICY_CLOCKGATING 1
239 #define PSB_PMPOLICY_POWERDOWN 2
240
241 #define PSB_PMSTATE_POWERUP 0
242 #define PSB_PMSTATE_CLOCKGATED 1
243 #define PSB_PMSTATE_POWERDOWN 2
244 #define PSB_PCIx_MSI_ADDR_LOC 0x94
245 #define PSB_PCIx_MSI_DATA_LOC 0x98
246
247 /* Medfield crystal settings */
248 #define KSEL_CRYSTAL_19 1
249 #define KSEL_BYPASS_19 5
250 #define KSEL_BYPASS_25 6
251 #define KSEL_BYPASS_83_100 7
252
253 struct opregion_header;
254 struct opregion_acpi;
255 struct opregion_swsci;
256 struct opregion_asle;
257
258 struct psb_intel_opregion {
259 struct opregion_header *header;
260 struct opregion_acpi *acpi;
261 struct opregion_swsci *swsci;
262 struct opregion_asle *asle;
263 void *vbt;
264 u32 __iomem *lid_state;
265 };
266
267 struct sdvo_device_mapping {
268 u8 initialized;
269 u8 dvo_port;
270 u8 slave_addr;
271 u8 dvo_wiring;
272 u8 i2c_pin;
273 u8 i2c_speed;
274 u8 ddc_pin;
275 };
276
277 struct intel_gmbus {
278 struct i2c_adapter adapter;
279 struct i2c_adapter *force_bit;
280 u32 reg0;
281 };
282
283 /*
284 * Register offset maps
285 */
286
287 struct psb_offset {
288 u32 fp0;
289 u32 fp1;
290 u32 cntr;
291 u32 conf;
292 u32 src;
293 u32 dpll;
294 u32 dpll_md;
295 u32 htotal;
296 u32 hblank;
297 u32 hsync;
298 u32 vtotal;
299 u32 vblank;
300 u32 vsync;
301 u32 stride;
302 u32 size;
303 u32 pos;
304 u32 surf;
305 u32 addr;
306 u32 base;
307 u32 status;
308 u32 linoff;
309 u32 tileoff;
310 u32 palette;
311 };
312
313 /*
314 * Register save state. This is used to hold the context when the
315 * device is powered off. In the case of Oaktrail this can (but does not
316 * yet) include screen blank. Operations occuring during the save
317 * update the register cache instead.
318 */
319
320 /*
321 * Common status for pipes.
322 */
323 struct psb_pipe {
324 u32 fp0;
325 u32 fp1;
326 u32 cntr;
327 u32 conf;
328 u32 src;
329 u32 dpll;
330 u32 dpll_md;
331 u32 htotal;
332 u32 hblank;
333 u32 hsync;
334 u32 vtotal;
335 u32 vblank;
336 u32 vsync;
337 u32 stride;
338 u32 size;
339 u32 pos;
340 u32 base;
341 u32 surf;
342 u32 addr;
343 u32 status;
344 u32 linoff;
345 u32 tileoff;
346 u32 palette[256];
347 };
348
349 struct psb_state {
350 uint32_t saveVCLK_DIVISOR_VGA0;
351 uint32_t saveVCLK_DIVISOR_VGA1;
352 uint32_t saveVCLK_POST_DIV;
353 uint32_t saveVGACNTRL;
354 uint32_t saveADPA;
355 uint32_t saveLVDS;
356 uint32_t saveDVOA;
357 uint32_t saveDVOB;
358 uint32_t saveDVOC;
359 uint32_t savePP_ON;
360 uint32_t savePP_OFF;
361 uint32_t savePP_CONTROL;
362 uint32_t savePP_CYCLE;
363 uint32_t savePFIT_CONTROL;
364 uint32_t saveCLOCKGATING;
365 uint32_t saveDSPARB;
366 uint32_t savePFIT_AUTO_RATIOS;
367 uint32_t savePFIT_PGM_RATIOS;
368 uint32_t savePP_ON_DELAYS;
369 uint32_t savePP_OFF_DELAYS;
370 uint32_t savePP_DIVISOR;
371 uint32_t saveBCLRPAT_A;
372 uint32_t saveBCLRPAT_B;
373 uint32_t savePERF_MODE;
374 uint32_t saveDSPFW1;
375 uint32_t saveDSPFW2;
376 uint32_t saveDSPFW3;
377 uint32_t saveDSPFW4;
378 uint32_t saveDSPFW5;
379 uint32_t saveDSPFW6;
380 uint32_t saveCHICKENBIT;
381 uint32_t saveDSPACURSOR_CTRL;
382 uint32_t saveDSPBCURSOR_CTRL;
383 uint32_t saveDSPACURSOR_BASE;
384 uint32_t saveDSPBCURSOR_BASE;
385 uint32_t saveDSPACURSOR_POS;
386 uint32_t saveDSPBCURSOR_POS;
387 uint32_t saveOV_OVADD;
388 uint32_t saveOV_OGAMC0;
389 uint32_t saveOV_OGAMC1;
390 uint32_t saveOV_OGAMC2;
391 uint32_t saveOV_OGAMC3;
392 uint32_t saveOV_OGAMC4;
393 uint32_t saveOV_OGAMC5;
394 uint32_t saveOVC_OVADD;
395 uint32_t saveOVC_OGAMC0;
396 uint32_t saveOVC_OGAMC1;
397 uint32_t saveOVC_OGAMC2;
398 uint32_t saveOVC_OGAMC3;
399 uint32_t saveOVC_OGAMC4;
400 uint32_t saveOVC_OGAMC5;
401
402 /* DPST register save */
403 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
404 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
405 uint32_t savePWM_CONTROL_LOGIC;
406 };
407
408 struct medfield_state {
409 uint32_t saveMIPI;
410 uint32_t saveMIPI_C;
411
412 uint32_t savePFIT_CONTROL;
413 uint32_t savePFIT_PGM_RATIOS;
414 uint32_t saveHDMIPHYMISCCTL;
415 uint32_t saveHDMIB_CONTROL;
416 };
417
418 struct cdv_state {
419 uint32_t saveDSPCLK_GATE_D;
420 uint32_t saveRAMCLK_GATE_D;
421 uint32_t saveDSPARB;
422 uint32_t saveDSPFW[6];
423 uint32_t saveADPA;
424 uint32_t savePP_CONTROL;
425 uint32_t savePFIT_PGM_RATIOS;
426 uint32_t saveLVDS;
427 uint32_t savePFIT_CONTROL;
428 uint32_t savePP_ON_DELAYS;
429 uint32_t savePP_OFF_DELAYS;
430 uint32_t savePP_CYCLE;
431 uint32_t saveVGACNTRL;
432 uint32_t saveIER;
433 uint32_t saveIMR;
434 u8 saveLBB;
435 };
436
437 struct psb_save_area {
438 struct psb_pipe pipe[3];
439 uint32_t saveBSM;
440 uint32_t saveVBT;
441 union {
442 struct psb_state psb;
443 struct medfield_state mdfld;
444 struct cdv_state cdv;
445 };
446 uint32_t saveBLC_PWM_CTL2;
447 uint32_t saveBLC_PWM_CTL;
448 };
449
450 struct psb_ops;
451
452 #define PSB_NUM_PIPE 3
453
454 struct drm_psb_private {
455 struct drm_device *dev;
456 const struct psb_ops *ops;
457 const struct psb_offset *regmap;
458
459 struct child_device_config *child_dev;
460 int child_dev_num;
461
462 struct psb_gtt gtt;
463
464 /* GTT Memory manager */
465 struct psb_gtt_mm *gtt_mm;
466 struct page *scratch_page;
467 u32 __iomem *gtt_map;
468 uint32_t stolen_base;
469 u8 __iomem *vram_addr;
470 unsigned long vram_stolen_size;
471 int gtt_initialized;
472 u16 gmch_ctrl; /* Saved GTT setup */
473 u32 pge_ctl;
474
475 struct mutex gtt_mutex;
476 struct resource *gtt_mem; /* Our PCI resource */
477
478 struct psb_mmu_driver *mmu;
479 struct psb_mmu_pd *pf_pd;
480
481 /*
482 * Register base
483 */
484
485 uint8_t __iomem *sgx_reg;
486 uint8_t __iomem *vdc_reg;
487 uint32_t gatt_free_offset;
488
489 /*
490 * Fencing / irq.
491 */
492
493 uint32_t vdc_irq_mask;
494 uint32_t pipestat[PSB_NUM_PIPE];
495
496 spinlock_t irqmask_lock;
497
498 /*
499 * Power
500 */
501
502 bool suspended;
503 bool display_power;
504 int display_count;
505
506 /*
507 * Modesetting
508 */
509 struct psb_intel_mode_device mode_dev;
510 bool modeset; /* true if we have done the mode_device setup */
511
512 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
513 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
514 uint32_t num_pipe;
515
516 /*
517 * OSPM info (Power management base) (can go ?)
518 */
519 uint32_t ospm_base;
520
521 /*
522 * Sizes info
523 */
524
525 u32 fuse_reg_value;
526 u32 video_device_fuse;
527
528 /* PCI revision ID for B0:D2:F0 */
529 uint8_t platform_rev_id;
530
531 /* gmbus */
532 struct intel_gmbus *gmbus;
533
534 /* Used by SDVO */
535 int crt_ddc_pin;
536 /* FIXME: The mappings should be parsed from bios but for now we can
537 pretend there are no mappings available */
538 struct sdvo_device_mapping sdvo_mappings[2];
539 u32 hotplug_supported_mask;
540 struct drm_property *broadcast_rgb_property;
541 struct drm_property *force_audio_property;
542
543 /*
544 * LVDS info
545 */
546 int backlight_duty_cycle; /* restore backlight to this value */
547 bool panel_wants_dither;
548 struct drm_display_mode *panel_fixed_mode;
549 struct drm_display_mode *lfp_lvds_vbt_mode;
550 struct drm_display_mode *sdvo_lvds_vbt_mode;
551
552 struct bdb_lvds_backlight *lvds_bl; /* LVDS backlight info from VBT */
553 struct psb_intel_i2c_chan *lvds_i2c_bus; /* FIXME: Remove this? */
554
555 /* Feature bits from the VBIOS */
556 unsigned int int_tv_support:1;
557 unsigned int lvds_dither:1;
558 unsigned int lvds_vbt:1;
559 unsigned int int_crt_support:1;
560 unsigned int lvds_use_ssc:1;
561 int lvds_ssc_freq;
562 bool is_lvds_on;
563 bool is_mipi_on;
564 u32 mipi_ctrl_display;
565
566 unsigned int core_freq;
567 uint32_t iLVDS_enable;
568
569 /* Runtime PM state */
570 int rpm_enabled;
571
572 /* MID specific */
573 bool has_gct;
574 struct oaktrail_gct_data gct_data;
575
576 /* Oaktrail HDMI state */
577 struct oaktrail_hdmi_dev *hdmi_priv;
578
579 /*
580 * Register state
581 */
582
583 struct psb_save_area regs;
584
585 /* MSI reg save */
586 uint32_t msi_addr;
587 uint32_t msi_data;
588
589 /*
590 * Hotplug handling
591 */
592
593 struct work_struct hotplug_work;
594
595 /*
596 * LID-Switch
597 */
598 spinlock_t lid_lock;
599 struct timer_list lid_timer;
600 struct psb_intel_opregion opregion;
601 u32 lid_last_state;
602
603 /*
604 * Watchdog
605 */
606
607 uint32_t apm_reg;
608 uint16_t apm_base;
609
610 /*
611 * Used for modifying backlight from
612 * xrandr -- consider removing and using HAL instead
613 */
614 struct backlight_device *backlight_device;
615 struct drm_property *backlight_property;
616 bool backlight_enabled;
617 int backlight_level;
618 uint32_t blc_adj1;
619 uint32_t blc_adj2;
620
621 void *fbdev;
622
623 /* 2D acceleration */
624 spinlock_t lock_2d;
625
626 /*
627 * Panel brightness
628 */
629 int brightness;
630 int brightness_adjusted;
631
632 bool dsr_enable;
633 u32 dsr_fb_update;
634 bool dpi_panel_on[3];
635 void *dsi_configs[2];
636 u32 bpp;
637 u32 bpp2;
638
639 u32 pipeconf[3];
640 u32 dspcntr[3];
641
642 int mdfld_panel_id;
643
644 bool dplla_96mhz; /* DPLL data from the VBT */
645
646 struct {
647 int rate;
648 int lanes;
649 int preemphasis;
650 int vswing;
651
652 bool initialized;
653 bool support;
654 int bpp;
655 struct edp_power_seq pps;
656 } edp;
657 uint8_t panel_type;
658 };
659
660
661 /*
662 * Operations for each board type
663 */
664
665 struct psb_ops {
666 const char *name;
667 unsigned int accel_2d:1;
668 int pipes; /* Number of output pipes */
669 int crtcs; /* Number of CRTCs */
670 int sgx_offset; /* Base offset of SGX device */
671 int hdmi_mask; /* Mask of HDMI CRTCs */
672 int lvds_mask; /* Mask of LVDS CRTCs */
673 int cursor_needs_phys; /* If cursor base reg need physical address */
674
675 /* Sub functions */
676 struct drm_crtc_helper_funcs const *crtc_helper;
677 struct drm_crtc_funcs const *crtc_funcs;
678
679 /* Setup hooks */
680 int (*chip_setup)(struct drm_device *dev);
681 void (*chip_teardown)(struct drm_device *dev);
682 /* Optional helper caller after modeset */
683 void (*errata)(struct drm_device *dev);
684
685 /* Display management hooks */
686 int (*output_init)(struct drm_device *dev);
687 int (*hotplug)(struct drm_device *dev);
688 void (*hotplug_enable)(struct drm_device *dev, bool on);
689 /* Power management hooks */
690 void (*init_pm)(struct drm_device *dev);
691 int (*save_regs)(struct drm_device *dev);
692 int (*restore_regs)(struct drm_device *dev);
693 int (*power_up)(struct drm_device *dev);
694 int (*power_down)(struct drm_device *dev);
695
696 void (*lvds_bl_power)(struct drm_device *dev, bool on);
697 #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
698 /* Backlight */
699 int (*backlight_init)(struct drm_device *dev);
700 #endif
701 int i2c_bus; /* I2C bus identifier for Moorestown */
702 };
703
704
705
706 struct psb_mmu_driver;
707
708 extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
709 extern int drm_pick_crtcs(struct drm_device *dev);
710
psb_priv(struct drm_device * dev)711 static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
712 {
713 return (struct drm_psb_private *) dev->dev_private;
714 }
715
716 /*
717 * MMU stuff.
718 */
719
720 extern struct psb_mmu_driver *psb_mmu_driver_init(uint8_t __iomem * registers,
721 int trap_pagefaults,
722 int invalid_type,
723 struct drm_psb_private *dev_priv);
724 extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver);
725 extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver
726 *driver);
727 extern void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd, uint32_t mmu_offset,
728 uint32_t gtt_start, uint32_t gtt_pages);
729 extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver,
730 int trap_pagefaults,
731 int invalid_type);
732 extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd);
733 extern void psb_mmu_flush(struct psb_mmu_driver *driver, int rc_prot);
734 extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd,
735 unsigned long address,
736 uint32_t num_pages);
737 extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd,
738 uint32_t start_pfn,
739 unsigned long address,
740 uint32_t num_pages, int type);
741 extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual,
742 unsigned long *pfn);
743
744 /*
745 * Enable / disable MMU for different requestors.
746 */
747
748
749 extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context);
750 extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages,
751 unsigned long address, uint32_t num_pages,
752 uint32_t desired_tile_stride,
753 uint32_t hw_tile_stride, int type);
754 extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd,
755 unsigned long address, uint32_t num_pages,
756 uint32_t desired_tile_stride,
757 uint32_t hw_tile_stride);
758 /*
759 *psb_irq.c
760 */
761
762 extern irqreturn_t psb_irq_handler(DRM_IRQ_ARGS);
763 extern int psb_irq_enable_dpst(struct drm_device *dev);
764 extern int psb_irq_disable_dpst(struct drm_device *dev);
765 extern void psb_irq_preinstall(struct drm_device *dev);
766 extern int psb_irq_postinstall(struct drm_device *dev);
767 extern void psb_irq_uninstall(struct drm_device *dev);
768 extern void psb_irq_turn_on_dpst(struct drm_device *dev);
769 extern void psb_irq_turn_off_dpst(struct drm_device *dev);
770
771 extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
772 extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
773 extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
774 extern int psb_enable_vblank(struct drm_device *dev, int crtc);
775 extern void psb_disable_vblank(struct drm_device *dev, int crtc);
776 void
777 psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
778
779 void
780 psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
781
782 extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
783
784 /*
785 * framebuffer.c
786 */
787 extern int psbfb_probed(struct drm_device *dev);
788 extern int psbfb_remove(struct drm_device *dev,
789 struct drm_framebuffer *fb);
790 /*
791 * accel_2d.c
792 */
793 extern void psbfb_copyarea(struct fb_info *info,
794 const struct fb_copyarea *region);
795 extern int psbfb_sync(struct fb_info *info);
796 extern void psb_spank(struct drm_psb_private *dev_priv);
797
798 /*
799 * psb_reset.c
800 */
801
802 extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
803 extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
804 extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
805
806 /* modesetting */
807 extern void psb_modeset_init(struct drm_device *dev);
808 extern void psb_modeset_cleanup(struct drm_device *dev);
809 extern int psb_fbdev_init(struct drm_device *dev);
810
811 /* backlight.c */
812 int gma_backlight_init(struct drm_device *dev);
813 void gma_backlight_exit(struct drm_device *dev);
814 void gma_backlight_disable(struct drm_device *dev);
815 void gma_backlight_enable(struct drm_device *dev);
816 void gma_backlight_set(struct drm_device *dev, int v);
817
818 /* oaktrail_crtc.c */
819 extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
820
821 /* oaktrail_lvds.c */
822 extern void oaktrail_lvds_init(struct drm_device *dev,
823 struct psb_intel_mode_device *mode_dev);
824
825 /* psb_intel_display.c */
826 extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
827 extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
828
829 /* psb_intel_lvds.c */
830 extern const struct drm_connector_helper_funcs
831 psb_intel_lvds_connector_helper_funcs;
832 extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
833
834 /* gem.c */
835 extern int psb_gem_init_object(struct drm_gem_object *obj);
836 extern void psb_gem_free_object(struct drm_gem_object *obj);
837 extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
838 struct drm_file *file);
839 extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
840 struct drm_mode_create_dumb *args);
841 extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
842 uint32_t handle);
843 extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
844 uint32_t handle, uint64_t *offset);
845 extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
846 extern int psb_gem_create_ioctl(struct drm_device *dev, void *data,
847 struct drm_file *file);
848 extern int psb_gem_mmap_ioctl(struct drm_device *dev, void *data,
849 struct drm_file *file);
850
851 /* psb_device.c */
852 extern const struct psb_ops psb_chip_ops;
853
854 /* oaktrail_device.c */
855 extern const struct psb_ops oaktrail_chip_ops;
856
857 /* mdlfd_device.c */
858 extern const struct psb_ops mdfld_chip_ops;
859
860 /* cdv_device.c */
861 extern const struct psb_ops cdv_chip_ops;
862
863 /*
864 * Debug print bits setting
865 */
866 #define PSB_D_GENERAL (1 << 0)
867 #define PSB_D_INIT (1 << 1)
868 #define PSB_D_IRQ (1 << 2)
869 #define PSB_D_ENTRY (1 << 3)
870 /* debug the get H/V BP/FP count */
871 #define PSB_D_HV (1 << 4)
872 #define PSB_D_DBI_BF (1 << 5)
873 #define PSB_D_PM (1 << 6)
874 #define PSB_D_RENDER (1 << 7)
875 #define PSB_D_REG (1 << 8)
876 #define PSB_D_MSVDX (1 << 9)
877 #define PSB_D_TOPAZ (1 << 10)
878
879 extern int drm_idle_check_interval;
880
881 /*
882 * Utilities
883 */
884
MRST_MSG_READ32(uint port,uint offset)885 static inline u32 MRST_MSG_READ32(uint port, uint offset)
886 {
887 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
888 uint32_t ret_val = 0;
889 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
890 pci_write_config_dword(pci_root, 0xD0, mcr);
891 pci_read_config_dword(pci_root, 0xD4, &ret_val);
892 pci_dev_put(pci_root);
893 return ret_val;
894 }
MRST_MSG_WRITE32(uint port,uint offset,u32 value)895 static inline void MRST_MSG_WRITE32(uint port, uint offset, u32 value)
896 {
897 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
898 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
899 pci_write_config_dword(pci_root, 0xD4, value);
900 pci_write_config_dword(pci_root, 0xD0, mcr);
901 pci_dev_put(pci_root);
902 }
MDFLD_MSG_READ32(uint port,uint offset)903 static inline u32 MDFLD_MSG_READ32(uint port, uint offset)
904 {
905 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
906 uint32_t ret_val = 0;
907 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
908 pci_write_config_dword(pci_root, 0xD0, mcr);
909 pci_read_config_dword(pci_root, 0xD4, &ret_val);
910 pci_dev_put(pci_root);
911 return ret_val;
912 }
MDFLD_MSG_WRITE32(uint port,uint offset,u32 value)913 static inline void MDFLD_MSG_WRITE32(uint port, uint offset, u32 value)
914 {
915 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
916 struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
917 pci_write_config_dword(pci_root, 0xD4, value);
918 pci_write_config_dword(pci_root, 0xD0, mcr);
919 pci_dev_put(pci_root);
920 }
921
REGISTER_READ(struct drm_device * dev,uint32_t reg)922 static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
923 {
924 struct drm_psb_private *dev_priv = dev->dev_private;
925 return ioread32(dev_priv->vdc_reg + reg);
926 }
927
928 #define REG_READ(reg) REGISTER_READ(dev, (reg))
929
REGISTER_WRITE(struct drm_device * dev,uint32_t reg,uint32_t val)930 static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
931 uint32_t val)
932 {
933 struct drm_psb_private *dev_priv = dev->dev_private;
934 iowrite32((val), dev_priv->vdc_reg + (reg));
935 }
936
937 #define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
938
REGISTER_WRITE16(struct drm_device * dev,uint32_t reg,uint32_t val)939 static inline void REGISTER_WRITE16(struct drm_device *dev,
940 uint32_t reg, uint32_t val)
941 {
942 struct drm_psb_private *dev_priv = dev->dev_private;
943 iowrite16((val), dev_priv->vdc_reg + (reg));
944 }
945
946 #define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
947
REGISTER_WRITE8(struct drm_device * dev,uint32_t reg,uint32_t val)948 static inline void REGISTER_WRITE8(struct drm_device *dev,
949 uint32_t reg, uint32_t val)
950 {
951 struct drm_psb_private *dev_priv = dev->dev_private;
952 iowrite8((val), dev_priv->vdc_reg + (reg));
953 }
954
955 #define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
956
957 #define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
958 #define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
959
960 /* #define TRAP_SGX_PM_FAULT 1 */
961 #ifdef TRAP_SGX_PM_FAULT
962 #define PSB_RSGX32(_offs) \
963 ({ \
964 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
965 printk(KERN_ERR \
966 "access sgx when it's off!! (READ) %s, %d\n", \
967 __FILE__, __LINE__); \
968 melay(1000); \
969 } \
970 ioread32(dev_priv->sgx_reg + (_offs)); \
971 })
972 #else
973 #define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
974 #endif
975 #define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
976
977 #define MSVDX_REG_DUMP 0
978
979 #define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
980 #define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
981
982 #endif
983