1 /* 2 * Copyright (c) 2005-2010 Brocade Communications Systems, Inc. 3 * All rights reserved 4 * www.brocade.com 5 * 6 * Linux driver for Brocade Fibre Channel Host Bus Adapter. 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License (GPL) Version 2 as 10 * published by the Free Software Foundation 11 * 12 * This program is distributed in the hope that it will be useful, but 13 * WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * General Public License for more details. 16 */ 17 18 #ifndef __BFA_DEFS_H__ 19 #define __BFA_DEFS_H__ 20 21 #include "bfa_fc.h" 22 #include "bfad_drv.h" 23 24 #define BFA_MFG_SERIALNUM_SIZE 11 25 #define STRSZ(_n) (((_n) + 4) & ~3) 26 27 /* 28 * Manufacturing card type 29 */ 30 enum { 31 BFA_MFG_TYPE_CB_MAX = 825, /* Crossbow card type max */ 32 BFA_MFG_TYPE_FC8P2 = 825, /* 8G 2port FC card */ 33 BFA_MFG_TYPE_FC8P1 = 815, /* 8G 1port FC card */ 34 BFA_MFG_TYPE_FC4P2 = 425, /* 4G 2port FC card */ 35 BFA_MFG_TYPE_FC4P1 = 415, /* 4G 1port FC card */ 36 BFA_MFG_TYPE_CNA10P2 = 1020, /* 10G 2port CNA card */ 37 BFA_MFG_TYPE_CNA10P1 = 1010, /* 10G 1port CNA card */ 38 BFA_MFG_TYPE_JAYHAWK = 804, /* Jayhawk mezz card */ 39 BFA_MFG_TYPE_WANCHESE = 1007, /* Wanchese mezz card */ 40 BFA_MFG_TYPE_ASTRA = 807, /* Astra mezz card */ 41 BFA_MFG_TYPE_LIGHTNING_P0 = 902, /* Lightning mezz card - old */ 42 BFA_MFG_TYPE_LIGHTNING = 1741, /* Lightning mezz card */ 43 BFA_MFG_TYPE_PROWLER_F = 1560, /* Prowler FC only cards */ 44 BFA_MFG_TYPE_PROWLER_N = 1410, /* Prowler NIC only cards */ 45 BFA_MFG_TYPE_PROWLER_C = 1710, /* Prowler CNA only cards */ 46 BFA_MFG_TYPE_PROWLER_D = 1860, /* Prowler Dual cards */ 47 BFA_MFG_TYPE_CHINOOK = 1867, /* Chinook cards */ 48 BFA_MFG_TYPE_INVALID = 0, /* Invalid card type */ 49 }; 50 51 #pragma pack(1) 52 53 /* 54 * Check if Mezz card 55 */ 56 #define bfa_mfg_is_mezz(type) (( \ 57 (type) == BFA_MFG_TYPE_JAYHAWK || \ 58 (type) == BFA_MFG_TYPE_WANCHESE || \ 59 (type) == BFA_MFG_TYPE_ASTRA || \ 60 (type) == BFA_MFG_TYPE_LIGHTNING_P0 || \ 61 (type) == BFA_MFG_TYPE_LIGHTNING || \ 62 (type) == BFA_MFG_TYPE_CHINOOK)) 63 64 /* 65 * Check if the card having old wwn/mac handling 66 */ 67 #define bfa_mfg_is_old_wwn_mac_model(type) (( \ 68 (type) == BFA_MFG_TYPE_FC8P2 || \ 69 (type) == BFA_MFG_TYPE_FC8P1 || \ 70 (type) == BFA_MFG_TYPE_FC4P2 || \ 71 (type) == BFA_MFG_TYPE_FC4P1 || \ 72 (type) == BFA_MFG_TYPE_CNA10P2 || \ 73 (type) == BFA_MFG_TYPE_CNA10P1 || \ 74 (type) == BFA_MFG_TYPE_JAYHAWK || \ 75 (type) == BFA_MFG_TYPE_WANCHESE)) 76 77 #define bfa_mfg_increment_wwn_mac(m, i) \ 78 do { \ 79 u32 t = ((u32)(m)[0] << 16) | ((u32)(m)[1] << 8) | \ 80 (u32)(m)[2]; \ 81 t += (i); \ 82 (m)[0] = (t >> 16) & 0xFF; \ 83 (m)[1] = (t >> 8) & 0xFF; \ 84 (m)[2] = t & 0xFF; \ 85 } while (0) 86 87 /* 88 * VPD data length 89 */ 90 #define BFA_MFG_VPD_LEN 512 91 92 /* 93 * VPD vendor tag 94 */ 95 enum { 96 BFA_MFG_VPD_UNKNOWN = 0, /* vendor unknown */ 97 BFA_MFG_VPD_IBM = 1, /* vendor IBM */ 98 BFA_MFG_VPD_HP = 2, /* vendor HP */ 99 BFA_MFG_VPD_DELL = 3, /* vendor DELL */ 100 BFA_MFG_VPD_PCI_IBM = 0x08, /* PCI VPD IBM */ 101 BFA_MFG_VPD_PCI_HP = 0x10, /* PCI VPD HP */ 102 BFA_MFG_VPD_PCI_DELL = 0x20, /* PCI VPD DELL */ 103 BFA_MFG_VPD_PCI_BRCD = 0xf8, /* PCI VPD Brocade */ 104 }; 105 106 /* 107 * All numerical fields are in big-endian format. 108 */ 109 struct bfa_mfg_vpd_s { 110 u8 version; /* vpd data version */ 111 u8 vpd_sig[3]; /* characters 'V', 'P', 'D' */ 112 u8 chksum; /* u8 checksum */ 113 u8 vendor; /* vendor */ 114 u8 len; /* vpd data length excluding header */ 115 u8 rsv; 116 u8 data[BFA_MFG_VPD_LEN]; /* vpd data */ 117 }; 118 119 #pragma pack() 120 121 /* 122 * Status return values 123 */ 124 enum bfa_status { 125 BFA_STATUS_OK = 0, /* Success */ 126 BFA_STATUS_FAILED = 1, /* Operation failed */ 127 BFA_STATUS_EINVAL = 2, /* Invalid params Check input 128 * parameters */ 129 BFA_STATUS_ENOMEM = 3, /* Out of resources */ 130 BFA_STATUS_ETIMER = 5, /* Timer expired - Retry, if persists, 131 * contact support */ 132 BFA_STATUS_EPROTOCOL = 6, /* Protocol error */ 133 BFA_STATUS_SFP_UNSUPP = 10, /* Unsupported SFP - Replace SFP */ 134 BFA_STATUS_UNKNOWN_VFID = 11, /* VF_ID not found */ 135 BFA_STATUS_DATACORRUPTED = 12, /* Diag returned data corrupted */ 136 BFA_STATUS_DEVBUSY = 13, /* Device busy - Retry operation */ 137 BFA_STATUS_HDMA_FAILED = 16, /* Host dma failed contact support */ 138 BFA_STATUS_FLASH_BAD_LEN = 17, /* Flash bad length */ 139 BFA_STATUS_UNKNOWN_LWWN = 18, /* LPORT PWWN not found */ 140 BFA_STATUS_UNKNOWN_RWWN = 19, /* RPORT PWWN not found */ 141 BFA_STATUS_VPORT_EXISTS = 21, /* VPORT already exists */ 142 BFA_STATUS_VPORT_MAX = 22, /* Reached max VPORT supported limit */ 143 BFA_STATUS_UNSUPP_SPEED = 23, /* Invalid Speed Check speed setting */ 144 BFA_STATUS_INVLD_DFSZ = 24, /* Invalid Max data field size */ 145 BFA_STATUS_CMD_NOTSUPP = 26, /* Command/API not supported */ 146 BFA_STATUS_FABRIC_RJT = 29, /* Reject from attached fabric */ 147 BFA_STATUS_UNKNOWN_VWWN = 30, /* VPORT PWWN not found */ 148 BFA_STATUS_PORT_OFFLINE = 34, /* Port is not online */ 149 BFA_STATUS_VPORT_WWN_BP = 46, /* WWN is same as base port's WWN */ 150 BFA_STATUS_PORT_NOT_DISABLED = 47, /* Port not disabled disable port */ 151 BFA_STATUS_NO_FCPIM_NEXUS = 52, /* No FCP Nexus exists with the rport */ 152 BFA_STATUS_IOC_FAILURE = 56, /* IOC failure - Retry, if persists 153 * contact support */ 154 BFA_STATUS_INVALID_WWN = 57, /* Invalid WWN */ 155 BFA_STATUS_ADAPTER_ENABLED = 60, /* Adapter is not disabled */ 156 BFA_STATUS_IOC_NON_OP = 61, /* IOC is not operational */ 157 BFA_STATUS_VERSION_FAIL = 70, /* Application/Driver version mismatch */ 158 BFA_STATUS_DIAG_BUSY = 71, /* diag busy */ 159 BFA_STATUS_BEACON_ON = 72, /* Port Beacon already on */ 160 BFA_STATUS_ENOFSAVE = 78, /* No saved firmware trace */ 161 BFA_STATUS_IOC_DISABLED = 82, /* IOC is already disabled */ 162 BFA_STATUS_ERROR_TRL_ENABLED = 87, /* TRL is enabled */ 163 BFA_STATUS_ERROR_QOS_ENABLED = 88, /* QoS is enabled */ 164 BFA_STATUS_NO_SFP_DEV = 89, /* No SFP device check or replace SFP */ 165 BFA_STATUS_MEMTEST_FAILED = 90, /* Memory test failed contact support */ 166 BFA_STATUS_LEDTEST_OP = 109, /* LED test is operating */ 167 BFA_STATUS_INVALID_MAC = 134, /* Invalid MAC address */ 168 BFA_STATUS_CMD_NOTSUPP_CNA = 146, /* Command not supported for CNA */ 169 BFA_STATUS_PBC = 154, /* Operation not allowed for pre-boot 170 * configuration */ 171 BFA_STATUS_BAD_FWCFG = 156, /* Bad firmware configuration */ 172 BFA_STATUS_INVALID_VENDOR = 158, /* Invalid switch vendor */ 173 BFA_STATUS_SFP_NOT_READY = 159, /* SFP info is not ready. Retry */ 174 BFA_STATUS_TRUNK_ENABLED = 164, /* Trunk is already enabled on 175 * this adapter */ 176 BFA_STATUS_TRUNK_DISABLED = 165, /* Trunking is disabled on 177 * the adapter */ 178 BFA_STATUS_IOPROFILE_OFF = 175, /* IO profile OFF */ 179 BFA_STATUS_PHY_NOT_PRESENT = 183, /* PHY module not present */ 180 BFA_STATUS_FEATURE_NOT_SUPPORTED = 192, /* Feature not supported */ 181 BFA_STATUS_ENTRY_EXISTS = 193, /* Entry already exists */ 182 BFA_STATUS_ENTRY_NOT_EXISTS = 194, /* Entry does not exist */ 183 BFA_STATUS_NO_CHANGE = 195, /* Feature already in that state */ 184 BFA_STATUS_FAA_ENABLED = 197, /* FAA is already enabled */ 185 BFA_STATUS_FAA_DISABLED = 198, /* FAA is already disabled */ 186 BFA_STATUS_FAA_ACQUIRED = 199, /* FAA is already acquired */ 187 BFA_STATUS_FAA_ACQ_ADDR = 200, /* Acquiring addr */ 188 BFA_STATUS_ERROR_TRUNK_ENABLED = 203, /* Trunk enabled on adapter */ 189 BFA_STATUS_MAX_ENTRY_REACHED = 212, /* MAX entry reached */ 190 BFA_STATUS_TOPOLOGY_LOOP = 230, /* Topology is set to Loop */ 191 BFA_STATUS_LOOP_UNSUPP_MEZZ = 231, /* Loop topology is not supported 192 * on mezz cards */ 193 BFA_STATUS_INVALID_BW = 233, /* Invalid bandwidth value */ 194 BFA_STATUS_QOS_BW_INVALID = 234, /* Invalid QOS bandwidth 195 * configuration */ 196 BFA_STATUS_DPORT_ENABLED = 235, /* D-port mode is already enabled */ 197 BFA_STATUS_DPORT_DISABLED = 236, /* D-port mode is already disabled */ 198 BFA_STATUS_CMD_NOTSUPP_MEZZ = 239, /* Cmd not supported for MEZZ card */ 199 BFA_STATUS_FRU_NOT_PRESENT = 240, /* fru module not present */ 200 BFA_STATUS_DPORT_ERR = 245, /* D-port mode is enabled */ 201 BFA_STATUS_MAX_VAL /* Unknown error code */ 202 }; 203 #define bfa_status_t enum bfa_status 204 205 enum bfa_eproto_status { 206 BFA_EPROTO_BAD_ACCEPT = 0, 207 BFA_EPROTO_UNKNOWN_RSP = 1 208 }; 209 #define bfa_eproto_status_t enum bfa_eproto_status 210 211 enum bfa_boolean { 212 BFA_FALSE = 0, 213 BFA_TRUE = 1 214 }; 215 #define bfa_boolean_t enum bfa_boolean 216 217 #define BFA_STRING_32 32 218 #define BFA_VERSION_LEN 64 219 220 /* 221 * ---------------------- adapter definitions ------------ 222 */ 223 224 /* 225 * BFA adapter level attributes. 226 */ 227 enum { 228 BFA_ADAPTER_SERIAL_NUM_LEN = STRSZ(BFA_MFG_SERIALNUM_SIZE), 229 /* 230 *!< adapter serial num length 231 */ 232 BFA_ADAPTER_MODEL_NAME_LEN = 16, /* model name length */ 233 BFA_ADAPTER_MODEL_DESCR_LEN = 128, /* model description length */ 234 BFA_ADAPTER_MFG_NAME_LEN = 8, /* manufacturer name length */ 235 BFA_ADAPTER_SYM_NAME_LEN = 64, /* adapter symbolic name length */ 236 BFA_ADAPTER_OS_TYPE_LEN = 64, /* adapter os type length */ 237 }; 238 239 struct bfa_adapter_attr_s { 240 char manufacturer[BFA_ADAPTER_MFG_NAME_LEN]; 241 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN]; 242 u32 card_type; 243 char model[BFA_ADAPTER_MODEL_NAME_LEN]; 244 char model_descr[BFA_ADAPTER_MODEL_DESCR_LEN]; 245 wwn_t pwwn; 246 char node_symname[FC_SYMNAME_MAX]; 247 char hw_ver[BFA_VERSION_LEN]; 248 char fw_ver[BFA_VERSION_LEN]; 249 char optrom_ver[BFA_VERSION_LEN]; 250 char os_type[BFA_ADAPTER_OS_TYPE_LEN]; 251 struct bfa_mfg_vpd_s vpd; 252 struct mac_s mac; 253 254 u8 nports; 255 u8 max_speed; 256 u8 prototype; 257 char asic_rev; 258 259 u8 pcie_gen; 260 u8 pcie_lanes_orig; 261 u8 pcie_lanes; 262 u8 cna_capable; 263 264 u8 is_mezz; 265 u8 trunk_capable; 266 u8 mfg_day; /* manufacturing day */ 267 u8 mfg_month; /* manufacturing month */ 268 u16 mfg_year; /* manufacturing year */ 269 u16 rsvd; 270 }; 271 272 /* 273 * ---------------------- IOC definitions ------------ 274 */ 275 276 enum { 277 BFA_IOC_DRIVER_LEN = 16, 278 BFA_IOC_CHIP_REV_LEN = 8, 279 }; 280 281 /* 282 * Driver and firmware versions. 283 */ 284 struct bfa_ioc_driver_attr_s { 285 char driver[BFA_IOC_DRIVER_LEN]; /* driver name */ 286 char driver_ver[BFA_VERSION_LEN]; /* driver version */ 287 char fw_ver[BFA_VERSION_LEN]; /* firmware version */ 288 char bios_ver[BFA_VERSION_LEN]; /* bios version */ 289 char efi_ver[BFA_VERSION_LEN]; /* EFI version */ 290 char ob_ver[BFA_VERSION_LEN]; /* openboot version */ 291 }; 292 293 /* 294 * IOC PCI device attributes 295 */ 296 struct bfa_ioc_pci_attr_s { 297 u16 vendor_id; /* PCI vendor ID */ 298 u16 device_id; /* PCI device ID */ 299 u16 ssid; /* subsystem ID */ 300 u16 ssvid; /* subsystem vendor ID */ 301 u32 pcifn; /* PCI device function */ 302 u32 rsvd; /* padding */ 303 char chip_rev[BFA_IOC_CHIP_REV_LEN]; /* chip revision */ 304 }; 305 306 /* 307 * IOC states 308 */ 309 enum bfa_ioc_state { 310 BFA_IOC_UNINIT = 1, /* IOC is in uninit state */ 311 BFA_IOC_RESET = 2, /* IOC is in reset state */ 312 BFA_IOC_SEMWAIT = 3, /* Waiting for IOC h/w semaphore */ 313 BFA_IOC_HWINIT = 4, /* IOC h/w is being initialized */ 314 BFA_IOC_GETATTR = 5, /* IOC is being configured */ 315 BFA_IOC_OPERATIONAL = 6, /* IOC is operational */ 316 BFA_IOC_INITFAIL = 7, /* IOC hardware failure */ 317 BFA_IOC_FAIL = 8, /* IOC heart-beat failure */ 318 BFA_IOC_DISABLING = 9, /* IOC is being disabled */ 319 BFA_IOC_DISABLED = 10, /* IOC is disabled */ 320 BFA_IOC_FWMISMATCH = 11, /* IOC f/w different from drivers */ 321 BFA_IOC_ENABLING = 12, /* IOC is being enabled */ 322 BFA_IOC_HWFAIL = 13, /* PCI mapping doesn't exist */ 323 BFA_IOC_ACQ_ADDR = 14, /* Acquiring addr from fabric */ 324 }; 325 326 /* 327 * IOC firmware stats 328 */ 329 struct bfa_fw_ioc_stats_s { 330 u32 enable_reqs; 331 u32 disable_reqs; 332 u32 get_attr_reqs; 333 u32 dbg_sync; 334 u32 dbg_dump; 335 u32 unknown_reqs; 336 }; 337 338 /* 339 * IOC driver stats 340 */ 341 struct bfa_ioc_drv_stats_s { 342 u32 ioc_isrs; 343 u32 ioc_enables; 344 u32 ioc_disables; 345 u32 ioc_hbfails; 346 u32 ioc_boots; 347 u32 stats_tmos; 348 u32 hb_count; 349 u32 disable_reqs; 350 u32 enable_reqs; 351 u32 disable_replies; 352 u32 enable_replies; 353 u32 rsvd; 354 }; 355 356 /* 357 * IOC statistics 358 */ 359 struct bfa_ioc_stats_s { 360 struct bfa_ioc_drv_stats_s drv_stats; /* driver IOC stats */ 361 struct bfa_fw_ioc_stats_s fw_stats; /* firmware IOC stats */ 362 }; 363 364 enum bfa_ioc_type_e { 365 BFA_IOC_TYPE_FC = 1, 366 BFA_IOC_TYPE_FCoE = 2, 367 BFA_IOC_TYPE_LL = 3, 368 }; 369 370 /* 371 * IOC attributes returned in queries 372 */ 373 struct bfa_ioc_attr_s { 374 enum bfa_ioc_type_e ioc_type; 375 enum bfa_ioc_state state; /* IOC state */ 376 struct bfa_adapter_attr_s adapter_attr; /* HBA attributes */ 377 struct bfa_ioc_driver_attr_s driver_attr; /* driver attr */ 378 struct bfa_ioc_pci_attr_s pci_attr; 379 u8 port_id; /* port number */ 380 u8 port_mode; /* bfa_mode_s */ 381 u8 cap_bm; /* capability */ 382 u8 port_mode_cfg; /* bfa_mode_s */ 383 u8 rsvd[4]; /* 64bit align */ 384 }; 385 386 /* 387 * AEN related definitions 388 */ 389 enum bfa_aen_category { 390 BFA_AEN_CAT_ADAPTER = 1, 391 BFA_AEN_CAT_PORT = 2, 392 BFA_AEN_CAT_LPORT = 3, 393 BFA_AEN_CAT_RPORT = 4, 394 BFA_AEN_CAT_ITNIM = 5, 395 BFA_AEN_CAT_AUDIT = 8, 396 BFA_AEN_CAT_IOC = 9, 397 }; 398 399 /* BFA adapter level events */ 400 enum bfa_adapter_aen_event { 401 BFA_ADAPTER_AEN_ADD = 1, /* New Adapter found event */ 402 BFA_ADAPTER_AEN_REMOVE = 2, /* Adapter removed event */ 403 }; 404 405 struct bfa_adapter_aen_data_s { 406 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN]; 407 u32 nports; /* Number of NPorts */ 408 wwn_t pwwn; /* WWN of one of its physical port */ 409 }; 410 411 /* BFA physical port Level events */ 412 enum bfa_port_aen_event { 413 BFA_PORT_AEN_ONLINE = 1, /* Physical Port online event */ 414 BFA_PORT_AEN_OFFLINE = 2, /* Physical Port offline event */ 415 BFA_PORT_AEN_RLIR = 3, /* RLIR event, not supported */ 416 BFA_PORT_AEN_SFP_INSERT = 4, /* SFP inserted event */ 417 BFA_PORT_AEN_SFP_REMOVE = 5, /* SFP removed event */ 418 BFA_PORT_AEN_SFP_POM = 6, /* SFP POM event */ 419 BFA_PORT_AEN_ENABLE = 7, /* Physical Port enable event */ 420 BFA_PORT_AEN_DISABLE = 8, /* Physical Port disable event */ 421 BFA_PORT_AEN_AUTH_ON = 9, /* Physical Port auth success event */ 422 BFA_PORT_AEN_AUTH_OFF = 10, /* Physical Port auth fail event */ 423 BFA_PORT_AEN_DISCONNECT = 11, /* Physical Port disconnect event */ 424 BFA_PORT_AEN_QOS_NEG = 12, /* Base Port QOS negotiation event */ 425 BFA_PORT_AEN_FABRIC_NAME_CHANGE = 13, /* Fabric Name/WWN change */ 426 BFA_PORT_AEN_SFP_ACCESS_ERROR = 14, /* SFP read error event */ 427 BFA_PORT_AEN_SFP_UNSUPPORT = 15, /* Unsupported SFP event */ 428 }; 429 430 enum bfa_port_aen_sfp_pom { 431 BFA_PORT_AEN_SFP_POM_GREEN = 1, /* Normal */ 432 BFA_PORT_AEN_SFP_POM_AMBER = 2, /* Warning */ 433 BFA_PORT_AEN_SFP_POM_RED = 3, /* Critical */ 434 BFA_PORT_AEN_SFP_POM_MAX = BFA_PORT_AEN_SFP_POM_RED 435 }; 436 437 struct bfa_port_aen_data_s { 438 wwn_t pwwn; /* WWN of the physical port */ 439 wwn_t fwwn; /* WWN of the fabric port */ 440 u32 phy_port_num; /* For SFP related events */ 441 u16 ioc_type; 442 u16 level; /* Only transitions will be informed */ 443 mac_t mac; /* MAC address of the ethernet port */ 444 u16 rsvd; 445 }; 446 447 /* BFA AEN logical port events */ 448 enum bfa_lport_aen_event { 449 BFA_LPORT_AEN_NEW = 1, /* LPort created event */ 450 BFA_LPORT_AEN_DELETE = 2, /* LPort deleted event */ 451 BFA_LPORT_AEN_ONLINE = 3, /* LPort online event */ 452 BFA_LPORT_AEN_OFFLINE = 4, /* LPort offline event */ 453 BFA_LPORT_AEN_DISCONNECT = 5, /* LPort disconnect event */ 454 BFA_LPORT_AEN_NEW_PROP = 6, /* VPort created event */ 455 BFA_LPORT_AEN_DELETE_PROP = 7, /* VPort deleted event */ 456 BFA_LPORT_AEN_NEW_STANDARD = 8, /* VPort created event */ 457 BFA_LPORT_AEN_DELETE_STANDARD = 9, /* VPort deleted event */ 458 BFA_LPORT_AEN_NPIV_DUP_WWN = 10, /* VPort with duplicate WWN */ 459 BFA_LPORT_AEN_NPIV_FABRIC_MAX = 11, /* Max NPIV in fabric/fport */ 460 BFA_LPORT_AEN_NPIV_UNKNOWN = 12, /* Unknown NPIV Error code */ 461 }; 462 463 struct bfa_lport_aen_data_s { 464 u16 vf_id; /* vf_id of this logical port */ 465 u16 roles; /* Logical port mode,IM/TM/IP etc */ 466 u32 rsvd; 467 wwn_t ppwwn; /* WWN of its physical port */ 468 wwn_t lpwwn; /* WWN of this logical port */ 469 }; 470 471 /* BFA ITNIM events */ 472 enum bfa_itnim_aen_event { 473 BFA_ITNIM_AEN_ONLINE = 1, /* Target online */ 474 BFA_ITNIM_AEN_OFFLINE = 2, /* Target offline */ 475 BFA_ITNIM_AEN_DISCONNECT = 3, /* Target disconnected */ 476 }; 477 478 struct bfa_itnim_aen_data_s { 479 u16 vf_id; /* vf_id of the IT nexus */ 480 u16 rsvd[3]; 481 wwn_t ppwwn; /* WWN of its physical port */ 482 wwn_t lpwwn; /* WWN of logical port */ 483 wwn_t rpwwn; /* WWN of remote(target) port */ 484 }; 485 486 /* BFA audit events */ 487 enum bfa_audit_aen_event { 488 BFA_AUDIT_AEN_AUTH_ENABLE = 1, 489 BFA_AUDIT_AEN_AUTH_DISABLE = 2, 490 BFA_AUDIT_AEN_FLASH_ERASE = 3, 491 BFA_AUDIT_AEN_FLASH_UPDATE = 4, 492 }; 493 494 struct bfa_audit_aen_data_s { 495 wwn_t pwwn; 496 int partition_inst; 497 int partition_type; 498 }; 499 500 /* BFA IOC level events */ 501 enum bfa_ioc_aen_event { 502 BFA_IOC_AEN_HBGOOD = 1, /* Heart Beat restore event */ 503 BFA_IOC_AEN_HBFAIL = 2, /* Heart Beat failure event */ 504 BFA_IOC_AEN_ENABLE = 3, /* IOC enabled event */ 505 BFA_IOC_AEN_DISABLE = 4, /* IOC disabled event */ 506 BFA_IOC_AEN_FWMISMATCH = 5, /* IOC firmware mismatch */ 507 BFA_IOC_AEN_FWCFG_ERROR = 6, /* IOC firmware config error */ 508 BFA_IOC_AEN_INVALID_VENDOR = 7, 509 BFA_IOC_AEN_INVALID_NWWN = 8, /* Zero NWWN */ 510 BFA_IOC_AEN_INVALID_PWWN = 9 /* Zero PWWN */ 511 }; 512 513 struct bfa_ioc_aen_data_s { 514 wwn_t pwwn; 515 u16 ioc_type; 516 mac_t mac; 517 }; 518 519 /* 520 * D-port states 521 * 522 */ 523 enum bfa_dport_state { 524 BFA_DPORT_ST_DISABLED = 0, /* D-port is Disabled */ 525 BFA_DPORT_ST_DISABLING = 1, /* D-port is Disabling */ 526 BFA_DPORT_ST_ENABLING = 2, /* D-port is Enabling */ 527 BFA_DPORT_ST_ENABLED = 3, /* D-port is Enabled */ 528 }; 529 530 /* 531 * ---------------------- mfg definitions ------------ 532 */ 533 534 /* 535 * Checksum size 536 */ 537 #define BFA_MFG_CHKSUM_SIZE 16 538 539 #define BFA_MFG_PARTNUM_SIZE 14 540 #define BFA_MFG_SUPPLIER_ID_SIZE 10 541 #define BFA_MFG_SUPPLIER_PARTNUM_SIZE 20 542 #define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20 543 #define BFA_MFG_SUPPLIER_REVISION_SIZE 4 544 /* 545 * Initial capability definition 546 */ 547 #define BFA_MFG_IC_FC 0x01 548 #define BFA_MFG_IC_ETH 0x02 549 550 /* 551 * Adapter capability mask definition 552 */ 553 #define BFA_CM_HBA 0x01 554 #define BFA_CM_CNA 0x02 555 #define BFA_CM_NIC 0x04 556 #define BFA_CM_FC16G 0x08 557 #define BFA_CM_SRIOV 0x10 558 #define BFA_CM_MEZZ 0x20 559 560 #pragma pack(1) 561 562 /* 563 * All numerical fields are in big-endian format. 564 */ 565 struct bfa_mfg_block_s { 566 u8 version; /*!< manufacturing block version */ 567 u8 mfg_sig[3]; /*!< characters 'M', 'F', 'G' */ 568 u16 mfgsize; /*!< mfg block size */ 569 u16 u16_chksum; /*!< old u16 checksum */ 570 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)]; 571 char brcd_partnum[STRSZ(BFA_MFG_PARTNUM_SIZE)]; 572 u8 mfg_day; /*!< manufacturing day */ 573 u8 mfg_month; /*!< manufacturing month */ 574 u16 mfg_year; /*!< manufacturing year */ 575 wwn_t mfg_wwn; /*!< wwn base for this adapter */ 576 u8 num_wwn; /*!< number of wwns assigned */ 577 u8 mfg_speeds; /*!< speeds allowed for this adapter */ 578 u8 rsv[2]; 579 char supplier_id[STRSZ(BFA_MFG_SUPPLIER_ID_SIZE)]; 580 char supplier_partnum[STRSZ(BFA_MFG_SUPPLIER_PARTNUM_SIZE)]; 581 char supplier_serialnum[STRSZ(BFA_MFG_SUPPLIER_SERIALNUM_SIZE)]; 582 char supplier_revision[STRSZ(BFA_MFG_SUPPLIER_REVISION_SIZE)]; 583 mac_t mfg_mac; /*!< base mac address */ 584 u8 num_mac; /*!< number of mac addresses */ 585 u8 rsv2; 586 u32 card_type; /*!< card type */ 587 char cap_nic; /*!< capability nic */ 588 char cap_cna; /*!< capability cna */ 589 char cap_hba; /*!< capability hba */ 590 char cap_fc16g; /*!< capability fc 16g */ 591 char cap_sriov; /*!< capability sriov */ 592 char cap_mezz; /*!< capability mezz */ 593 u8 rsv3; 594 u8 mfg_nports; /*!< number of ports */ 595 char media[8]; /*!< xfi/xaui */ 596 char initial_mode[8]; /*!< initial mode: hba/cna/nic */ 597 u8 rsv4[84]; 598 u8 md5_chksum[BFA_MFG_CHKSUM_SIZE]; /*!< md5 checksum */ 599 }; 600 601 #pragma pack() 602 603 /* 604 * ---------------------- pci definitions ------------ 605 */ 606 607 /* 608 * PCI device and vendor ID information 609 */ 610 enum { 611 BFA_PCI_VENDOR_ID_BROCADE = 0x1657, 612 BFA_PCI_DEVICE_ID_FC_8G2P = 0x13, 613 BFA_PCI_DEVICE_ID_FC_8G1P = 0x17, 614 BFA_PCI_DEVICE_ID_CT = 0x14, 615 BFA_PCI_DEVICE_ID_CT_FC = 0x21, 616 BFA_PCI_DEVICE_ID_CT2 = 0x22, 617 }; 618 619 #define bfa_asic_id_cb(__d) \ 620 ((__d) == BFA_PCI_DEVICE_ID_FC_8G2P || \ 621 (__d) == BFA_PCI_DEVICE_ID_FC_8G1P) 622 #define bfa_asic_id_ct(__d) \ 623 ((__d) == BFA_PCI_DEVICE_ID_CT || \ 624 (__d) == BFA_PCI_DEVICE_ID_CT_FC) 625 #define bfa_asic_id_ct2(__d) ((__d) == BFA_PCI_DEVICE_ID_CT2) 626 #define bfa_asic_id_ctc(__d) \ 627 (bfa_asic_id_ct(__d) || bfa_asic_id_ct2(__d)) 628 629 /* 630 * PCI sub-system device and vendor ID information 631 */ 632 enum { 633 BFA_PCI_FCOE_SSDEVICE_ID = 0x14, 634 BFA_PCI_CT2_SSID_FCoE = 0x22, 635 BFA_PCI_CT2_SSID_ETH = 0x23, 636 BFA_PCI_CT2_SSID_FC = 0x24, 637 }; 638 639 /* 640 * Maximum number of device address ranges mapped through different BAR(s) 641 */ 642 #define BFA_PCI_ACCESS_RANGES 1 643 644 /* 645 * Port speed settings. Each specific speed is a bit field. Use multiple 646 * bits to specify speeds to be selected for auto-negotiation. 647 */ 648 enum bfa_port_speed { 649 BFA_PORT_SPEED_UNKNOWN = 0, 650 BFA_PORT_SPEED_1GBPS = 1, 651 BFA_PORT_SPEED_2GBPS = 2, 652 BFA_PORT_SPEED_4GBPS = 4, 653 BFA_PORT_SPEED_8GBPS = 8, 654 BFA_PORT_SPEED_10GBPS = 10, 655 BFA_PORT_SPEED_16GBPS = 16, 656 BFA_PORT_SPEED_AUTO = 0xf, 657 }; 658 #define bfa_port_speed_t enum bfa_port_speed 659 660 enum { 661 BFA_BOOT_BOOTLUN_MAX = 4, /* maximum boot lun per IOC */ 662 BFA_PREBOOT_BOOTLUN_MAX = 8, /* maximum preboot lun per IOC */ 663 }; 664 665 #define BOOT_CFG_REV1 1 666 #define BOOT_CFG_VLAN 1 667 668 /* 669 * Boot options setting. Boot options setting determines from where 670 * to get the boot lun information 671 */ 672 enum bfa_boot_bootopt { 673 BFA_BOOT_AUTO_DISCOVER = 0, /* Boot from blun provided by fabric */ 674 BFA_BOOT_STORED_BLUN = 1, /* Boot from bluns stored in flash */ 675 BFA_BOOT_FIRST_LUN = 2, /* Boot from first discovered blun */ 676 BFA_BOOT_PBC = 3, /* Boot from pbc configured blun */ 677 }; 678 679 #pragma pack(1) 680 /* 681 * Boot lun information. 682 */ 683 struct bfa_boot_bootlun_s { 684 wwn_t pwwn; /* port wwn of target */ 685 struct scsi_lun lun; /* 64-bit lun */ 686 }; 687 #pragma pack() 688 689 /* 690 * BOOT boot configuraton 691 */ 692 struct bfa_boot_cfg_s { 693 u8 version; 694 u8 rsvd1; 695 u16 chksum; 696 u8 enable; /* enable/disable SAN boot */ 697 u8 speed; /* boot speed settings */ 698 u8 topology; /* boot topology setting */ 699 u8 bootopt; /* bfa_boot_bootopt_t */ 700 u32 nbluns; /* number of boot luns */ 701 u32 rsvd2; 702 struct bfa_boot_bootlun_s blun[BFA_BOOT_BOOTLUN_MAX]; 703 struct bfa_boot_bootlun_s blun_disc[BFA_BOOT_BOOTLUN_MAX]; 704 }; 705 706 struct bfa_boot_pbc_s { 707 u8 enable; /* enable/disable SAN boot */ 708 u8 speed; /* boot speed settings */ 709 u8 topology; /* boot topology setting */ 710 u8 rsvd1; 711 u32 nbluns; /* number of boot luns */ 712 struct bfa_boot_bootlun_s pblun[BFA_PREBOOT_BOOTLUN_MAX]; 713 }; 714 715 struct bfa_ethboot_cfg_s { 716 u8 version; 717 u8 rsvd1; 718 u16 chksum; 719 u8 enable; /* enable/disable Eth/PXE boot */ 720 u8 rsvd2; 721 u16 vlan; 722 }; 723 724 /* 725 * ASIC block configuration related structures 726 */ 727 #define BFA_ABLK_MAX_PORTS 2 728 #define BFA_ABLK_MAX_PFS 16 729 #define BFA_ABLK_MAX 2 730 731 #pragma pack(1) 732 enum bfa_mode_s { 733 BFA_MODE_HBA = 1, 734 BFA_MODE_CNA = 2, 735 BFA_MODE_NIC = 3 736 }; 737 738 struct bfa_adapter_cfg_mode_s { 739 u16 max_pf; 740 u16 max_vf; 741 enum bfa_mode_s mode; 742 }; 743 744 struct bfa_ablk_cfg_pf_s { 745 u16 pers; 746 u8 port_id; 747 u8 optrom; 748 u8 valid; 749 u8 sriov; 750 u8 max_vfs; 751 u8 rsvd[1]; 752 u16 num_qpairs; 753 u16 num_vectors; 754 u16 bw_min; 755 u16 bw_max; 756 }; 757 758 struct bfa_ablk_cfg_port_s { 759 u8 mode; 760 u8 type; 761 u8 max_pfs; 762 u8 rsvd[5]; 763 }; 764 765 struct bfa_ablk_cfg_inst_s { 766 u8 nports; 767 u8 max_pfs; 768 u8 rsvd[6]; 769 struct bfa_ablk_cfg_pf_s pf_cfg[BFA_ABLK_MAX_PFS]; 770 struct bfa_ablk_cfg_port_s port_cfg[BFA_ABLK_MAX_PORTS]; 771 }; 772 773 struct bfa_ablk_cfg_s { 774 struct bfa_ablk_cfg_inst_s inst[BFA_ABLK_MAX]; 775 }; 776 777 778 /* 779 * SFP module specific 780 */ 781 #define SFP_DIAGMON_SIZE 10 /* num bytes of diag monitor data */ 782 783 /* SFP state change notification event */ 784 #define BFA_SFP_SCN_REMOVED 0 785 #define BFA_SFP_SCN_INSERTED 1 786 #define BFA_SFP_SCN_POM 2 787 #define BFA_SFP_SCN_FAILED 3 788 #define BFA_SFP_SCN_UNSUPPORT 4 789 #define BFA_SFP_SCN_VALID 5 790 791 enum bfa_defs_sfp_media_e { 792 BFA_SFP_MEDIA_UNKNOWN = 0x00, 793 BFA_SFP_MEDIA_CU = 0x01, 794 BFA_SFP_MEDIA_LW = 0x02, 795 BFA_SFP_MEDIA_SW = 0x03, 796 BFA_SFP_MEDIA_EL = 0x04, 797 BFA_SFP_MEDIA_UNSUPPORT = 0x05, 798 }; 799 800 /* 801 * values for xmtr_tech above 802 */ 803 enum { 804 SFP_XMTR_TECH_CU = (1 << 0), /* copper FC-BaseT */ 805 SFP_XMTR_TECH_CP = (1 << 1), /* copper passive */ 806 SFP_XMTR_TECH_CA = (1 << 2), /* copper active */ 807 SFP_XMTR_TECH_LL = (1 << 3), /* longwave laser */ 808 SFP_XMTR_TECH_SL = (1 << 4), /* shortwave laser w/ OFC */ 809 SFP_XMTR_TECH_SN = (1 << 5), /* shortwave laser w/o OFC */ 810 SFP_XMTR_TECH_EL_INTRA = (1 << 6), /* elec intra-enclosure */ 811 SFP_XMTR_TECH_EL_INTER = (1 << 7), /* elec inter-enclosure */ 812 SFP_XMTR_TECH_LC = (1 << 8), /* longwave laser */ 813 SFP_XMTR_TECH_SA = (1 << 9) 814 }; 815 816 /* 817 * Serial ID: Data Fields -- Address A0h 818 * Basic ID field total 64 bytes 819 */ 820 struct sfp_srlid_base_s { 821 u8 id; /* 00: Identifier */ 822 u8 extid; /* 01: Extended Identifier */ 823 u8 connector; /* 02: Connector */ 824 u8 xcvr[8]; /* 03-10: Transceiver */ 825 u8 encoding; /* 11: Encoding */ 826 u8 br_norm; /* 12: BR, Nominal */ 827 u8 rate_id; /* 13: Rate Identifier */ 828 u8 len_km; /* 14: Length single mode km */ 829 u8 len_100m; /* 15: Length single mode 100m */ 830 u8 len_om2; /* 16: Length om2 fiber 10m */ 831 u8 len_om1; /* 17: Length om1 fiber 10m */ 832 u8 len_cu; /* 18: Length copper 1m */ 833 u8 len_om3; /* 19: Length om3 fiber 10m */ 834 u8 vendor_name[16];/* 20-35 */ 835 u8 unalloc1; 836 u8 vendor_oui[3]; /* 37-39 */ 837 u8 vendor_pn[16]; /* 40-55 */ 838 u8 vendor_rev[4]; /* 56-59 */ 839 u8 wavelen[2]; /* 60-61 */ 840 u8 unalloc2; 841 u8 cc_base; /* 63: check code for base id field */ 842 }; 843 844 /* 845 * Serial ID: Data Fields -- Address A0h 846 * Extended id field total 32 bytes 847 */ 848 struct sfp_srlid_ext_s { 849 u8 options[2]; 850 u8 br_max; 851 u8 br_min; 852 u8 vendor_sn[16]; 853 u8 date_code[8]; 854 u8 diag_mon_type; /* 92: Diagnostic Monitoring type */ 855 u8 en_options; 856 u8 sff_8472; 857 u8 cc_ext; 858 }; 859 860 /* 861 * Diagnostic: Data Fields -- Address A2h 862 * Diagnostic and control/status base field total 96 bytes 863 */ 864 struct sfp_diag_base_s { 865 /* 866 * Alarm and warning Thresholds 40 bytes 867 */ 868 u8 temp_high_alarm[2]; /* 00-01 */ 869 u8 temp_low_alarm[2]; /* 02-03 */ 870 u8 temp_high_warning[2]; /* 04-05 */ 871 u8 temp_low_warning[2]; /* 06-07 */ 872 873 u8 volt_high_alarm[2]; /* 08-09 */ 874 u8 volt_low_alarm[2]; /* 10-11 */ 875 u8 volt_high_warning[2]; /* 12-13 */ 876 u8 volt_low_warning[2]; /* 14-15 */ 877 878 u8 bias_high_alarm[2]; /* 16-17 */ 879 u8 bias_low_alarm[2]; /* 18-19 */ 880 u8 bias_high_warning[2]; /* 20-21 */ 881 u8 bias_low_warning[2]; /* 22-23 */ 882 883 u8 tx_pwr_high_alarm[2]; /* 24-25 */ 884 u8 tx_pwr_low_alarm[2]; /* 26-27 */ 885 u8 tx_pwr_high_warning[2]; /* 28-29 */ 886 u8 tx_pwr_low_warning[2]; /* 30-31 */ 887 888 u8 rx_pwr_high_alarm[2]; /* 32-33 */ 889 u8 rx_pwr_low_alarm[2]; /* 34-35 */ 890 u8 rx_pwr_high_warning[2]; /* 36-37 */ 891 u8 rx_pwr_low_warning[2]; /* 38-39 */ 892 893 u8 unallocate_1[16]; 894 895 /* 896 * ext_cal_const[36] 897 */ 898 u8 rx_pwr[20]; 899 u8 tx_i[4]; 900 u8 tx_pwr[4]; 901 u8 temp[4]; 902 u8 volt[4]; 903 u8 unallocate_2[3]; 904 u8 cc_dmi; 905 }; 906 907 /* 908 * Diagnostic: Data Fields -- Address A2h 909 * Diagnostic and control/status extended field total 24 bytes 910 */ 911 struct sfp_diag_ext_s { 912 u8 diag[SFP_DIAGMON_SIZE]; 913 u8 unalloc1[4]; 914 u8 status_ctl; 915 u8 rsvd; 916 u8 alarm_flags[2]; 917 u8 unalloc2[2]; 918 u8 warning_flags[2]; 919 u8 ext_status_ctl[2]; 920 }; 921 922 /* 923 * Diagnostic: Data Fields -- Address A2h 924 * General Use Fields: User Writable Table - Features's Control Registers 925 * Total 32 bytes 926 */ 927 struct sfp_usr_eeprom_s { 928 u8 rsvd1[2]; /* 128-129 */ 929 u8 ewrap; /* 130 */ 930 u8 rsvd2[2]; /* */ 931 u8 owrap; /* 133 */ 932 u8 rsvd3[2]; /* */ 933 u8 prbs; /* 136: PRBS 7 generator */ 934 u8 rsvd4[2]; /* */ 935 u8 tx_eqz_16; /* 139: TX Equalizer (16xFC) */ 936 u8 tx_eqz_8; /* 140: TX Equalizer (8xFC) */ 937 u8 rsvd5[2]; /* */ 938 u8 rx_emp_16; /* 143: RX Emphasis (16xFC) */ 939 u8 rx_emp_8; /* 144: RX Emphasis (8xFC) */ 940 u8 rsvd6[2]; /* */ 941 u8 tx_eye_adj; /* 147: TX eye Threshold Adjust */ 942 u8 rsvd7[3]; /* */ 943 u8 tx_eye_qctl; /* 151: TX eye Quality Control */ 944 u8 tx_eye_qres; /* 152: TX eye Quality Result */ 945 u8 rsvd8[2]; /* */ 946 u8 poh[3]; /* 155-157: Power On Hours */ 947 u8 rsvd9[2]; /* */ 948 }; 949 950 struct sfp_mem_s { 951 struct sfp_srlid_base_s srlid_base; 952 struct sfp_srlid_ext_s srlid_ext; 953 struct sfp_diag_base_s diag_base; 954 struct sfp_diag_ext_s diag_ext; 955 struct sfp_usr_eeprom_s usr_eeprom; 956 }; 957 958 /* 959 * transceiver codes (SFF-8472 Rev 10.2 Table 3.5) 960 */ 961 union sfp_xcvr_e10g_code_u { 962 u8 b; 963 struct { 964 #ifdef __BIG_ENDIAN 965 u8 e10g_unall:1; /* 10G Ethernet compliance */ 966 u8 e10g_lrm:1; 967 u8 e10g_lr:1; 968 u8 e10g_sr:1; 969 u8 ib_sx:1; /* Infiniband compliance */ 970 u8 ib_lx:1; 971 u8 ib_cu_a:1; 972 u8 ib_cu_p:1; 973 #else 974 u8 ib_cu_p:1; 975 u8 ib_cu_a:1; 976 u8 ib_lx:1; 977 u8 ib_sx:1; /* Infiniband compliance */ 978 u8 e10g_sr:1; 979 u8 e10g_lr:1; 980 u8 e10g_lrm:1; 981 u8 e10g_unall:1; /* 10G Ethernet compliance */ 982 #endif 983 } r; 984 }; 985 986 union sfp_xcvr_so1_code_u { 987 u8 b; 988 struct { 989 u8 escon:2; /* ESCON compliance code */ 990 u8 oc192_reach:1; /* SONET compliance code */ 991 u8 so_reach:2; 992 u8 oc48_reach:3; 993 } r; 994 }; 995 996 union sfp_xcvr_so2_code_u { 997 u8 b; 998 struct { 999 u8 reserved:1; 1000 u8 oc12_reach:3; /* OC12 reach */ 1001 u8 reserved1:1; 1002 u8 oc3_reach:3; /* OC3 reach */ 1003 } r; 1004 }; 1005 1006 union sfp_xcvr_eth_code_u { 1007 u8 b; 1008 struct { 1009 u8 base_px:1; 1010 u8 base_bx10:1; 1011 u8 e100base_fx:1; 1012 u8 e100base_lx:1; 1013 u8 e1000base_t:1; 1014 u8 e1000base_cx:1; 1015 u8 e1000base_lx:1; 1016 u8 e1000base_sx:1; 1017 } r; 1018 }; 1019 1020 struct sfp_xcvr_fc1_code_s { 1021 u8 link_len:5; /* FC link length */ 1022 u8 xmtr_tech2:3; 1023 u8 xmtr_tech1:7; /* FC transmitter technology */ 1024 u8 reserved1:1; 1025 }; 1026 1027 union sfp_xcvr_fc2_code_u { 1028 u8 b; 1029 struct { 1030 u8 tw_media:1; /* twin axial pair (tw) */ 1031 u8 tp_media:1; /* shielded twisted pair (sp) */ 1032 u8 mi_media:1; /* miniature coax (mi) */ 1033 u8 tv_media:1; /* video coax (tv) */ 1034 u8 m6_media:1; /* multimode, 62.5m (m6) */ 1035 u8 m5_media:1; /* multimode, 50m (m5) */ 1036 u8 reserved:1; 1037 u8 sm_media:1; /* single mode (sm) */ 1038 } r; 1039 }; 1040 1041 union sfp_xcvr_fc3_code_u { 1042 u8 b; 1043 struct { 1044 #ifdef __BIG_ENDIAN 1045 u8 rsv4:1; 1046 u8 mb800:1; /* 800 Mbytes/sec */ 1047 u8 mb1600:1; /* 1600 Mbytes/sec */ 1048 u8 mb400:1; /* 400 Mbytes/sec */ 1049 u8 rsv2:1; 1050 u8 mb200:1; /* 200 Mbytes/sec */ 1051 u8 rsv1:1; 1052 u8 mb100:1; /* 100 Mbytes/sec */ 1053 #else 1054 u8 mb100:1; /* 100 Mbytes/sec */ 1055 u8 rsv1:1; 1056 u8 mb200:1; /* 200 Mbytes/sec */ 1057 u8 rsv2:1; 1058 u8 mb400:1; /* 400 Mbytes/sec */ 1059 u8 mb1600:1; /* 1600 Mbytes/sec */ 1060 u8 mb800:1; /* 800 Mbytes/sec */ 1061 u8 rsv4:1; 1062 #endif 1063 } r; 1064 }; 1065 1066 struct sfp_xcvr_s { 1067 union sfp_xcvr_e10g_code_u e10g; 1068 union sfp_xcvr_so1_code_u so1; 1069 union sfp_xcvr_so2_code_u so2; 1070 union sfp_xcvr_eth_code_u eth; 1071 struct sfp_xcvr_fc1_code_s fc1; 1072 union sfp_xcvr_fc2_code_u fc2; 1073 union sfp_xcvr_fc3_code_u fc3; 1074 }; 1075 1076 /* 1077 * Flash module specific 1078 */ 1079 #define BFA_FLASH_PART_ENTRY_SIZE 32 /* partition entry size */ 1080 #define BFA_FLASH_PART_MAX 32 /* maximal # of partitions */ 1081 1082 enum bfa_flash_part_type { 1083 BFA_FLASH_PART_OPTROM = 1, /* option rom partition */ 1084 BFA_FLASH_PART_FWIMG = 2, /* firmware image partition */ 1085 BFA_FLASH_PART_FWCFG = 3, /* firmware tuneable config */ 1086 BFA_FLASH_PART_DRV = 4, /* IOC driver config */ 1087 BFA_FLASH_PART_BOOT = 5, /* boot config */ 1088 BFA_FLASH_PART_ASIC = 6, /* asic bootstrap configuration */ 1089 BFA_FLASH_PART_MFG = 7, /* manufacturing block partition */ 1090 BFA_FLASH_PART_OPTROM2 = 8, /* 2nd option rom partition */ 1091 BFA_FLASH_PART_VPD = 9, /* vpd data of OEM info */ 1092 BFA_FLASH_PART_PBC = 10, /* pre-boot config */ 1093 BFA_FLASH_PART_BOOTOVL = 11, /* boot overlay partition */ 1094 BFA_FLASH_PART_LOG = 12, /* firmware log partition */ 1095 BFA_FLASH_PART_PXECFG = 13, /* pxe boot config partition */ 1096 BFA_FLASH_PART_PXEOVL = 14, /* pxe boot overlay partition */ 1097 BFA_FLASH_PART_PORTCFG = 15, /* port cfg partition */ 1098 BFA_FLASH_PART_ASICBK = 16, /* asic backup partition */ 1099 }; 1100 1101 /* 1102 * flash partition attributes 1103 */ 1104 struct bfa_flash_part_attr_s { 1105 u32 part_type; /* partition type */ 1106 u32 part_instance; /* partition instance */ 1107 u32 part_off; /* partition offset */ 1108 u32 part_size; /* partition size */ 1109 u32 part_len; /* partition content length */ 1110 u32 part_status; /* partition status */ 1111 char rsv[BFA_FLASH_PART_ENTRY_SIZE - 24]; 1112 }; 1113 1114 /* 1115 * flash attributes 1116 */ 1117 struct bfa_flash_attr_s { 1118 u32 status; /* flash overall status */ 1119 u32 npart; /* num of partitions */ 1120 struct bfa_flash_part_attr_s part[BFA_FLASH_PART_MAX]; 1121 }; 1122 1123 /* 1124 * DIAG module specific 1125 */ 1126 #define LB_PATTERN_DEFAULT 0xB5B5B5B5 1127 #define QTEST_CNT_DEFAULT 10 1128 #define QTEST_PAT_DEFAULT LB_PATTERN_DEFAULT 1129 1130 struct bfa_diag_memtest_s { 1131 u8 algo; 1132 u8 rsvd[7]; 1133 }; 1134 1135 struct bfa_diag_memtest_result { 1136 u32 status; 1137 u32 addr; 1138 u32 exp; /* expect value read from reg */ 1139 u32 act; /* actually value read */ 1140 u32 err_status; /* error status reg */ 1141 u32 err_status1; /* extra error info reg */ 1142 u32 err_addr; /* error address reg */ 1143 u8 algo; 1144 u8 rsv[3]; 1145 }; 1146 1147 struct bfa_diag_loopback_result_s { 1148 u32 numtxmfrm; /* no. of transmit frame */ 1149 u32 numosffrm; /* no. of outstanding frame */ 1150 u32 numrcvfrm; /* no. of received good frame */ 1151 u32 badfrminf; /* mis-match info */ 1152 u32 badfrmnum; /* mis-match fram number */ 1153 u8 status; /* loopback test result */ 1154 u8 rsvd[3]; 1155 }; 1156 1157 struct bfa_diag_ledtest_s { 1158 u32 cmd; /* bfa_led_op_t */ 1159 u32 color; /* bfa_led_color_t */ 1160 u16 freq; /* no. of blinks every 10 secs */ 1161 u8 led; /* bitmap of LEDs to be tested */ 1162 u8 rsvd[5]; 1163 }; 1164 1165 struct bfa_diag_loopback_s { 1166 u32 loopcnt; 1167 u32 pattern; 1168 u8 lb_mode; /* bfa_port_opmode_t */ 1169 u8 speed; /* bfa_port_speed_t */ 1170 u8 rsvd[2]; 1171 }; 1172 1173 /* 1174 * PHY module specific 1175 */ 1176 enum bfa_phy_status_e { 1177 BFA_PHY_STATUS_GOOD = 0, /* phy is good */ 1178 BFA_PHY_STATUS_NOT_PRESENT = 1, /* phy does not exist */ 1179 BFA_PHY_STATUS_BAD = 2, /* phy is bad */ 1180 }; 1181 1182 /* 1183 * phy attributes for phy query 1184 */ 1185 struct bfa_phy_attr_s { 1186 u32 status; /* phy present/absent status */ 1187 u32 length; /* firmware length */ 1188 u32 fw_ver; /* firmware version */ 1189 u32 an_status; /* AN status */ 1190 u32 pma_pmd_status; /* PMA/PMD link status */ 1191 u32 pma_pmd_signal; /* PMA/PMD signal detect */ 1192 u32 pcs_status; /* PCS link status */ 1193 }; 1194 1195 /* 1196 * phy stats 1197 */ 1198 struct bfa_phy_stats_s { 1199 u32 status; /* phy stats status */ 1200 u32 link_breaks; /* Num of link breaks after linkup */ 1201 u32 pma_pmd_fault; /* NPMA/PMD fault */ 1202 u32 pcs_fault; /* PCS fault */ 1203 u32 speed_neg; /* Num of speed negotiation */ 1204 u32 tx_eq_training; /* Num of TX EQ training */ 1205 u32 tx_eq_timeout; /* Num of TX EQ timeout */ 1206 u32 crc_error; /* Num of CRC errors */ 1207 }; 1208 1209 #pragma pack() 1210 1211 #endif /* __BFA_DEFS_H__ */ 1212