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Searched refs:tiling_flags (Results 1 – 16 of 16) sorted by relevance

/drivers/gpu/drm/radeon/
Dradeon_object.c382 lobj->tiling_flags = bo->tiling_flags; in radeon_bo_list_validate()
403 if (!bo->tiling_flags) in radeon_bo_get_surface_reg()
442 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, in radeon_bo_get_surface_reg()
464 uint32_t tiling_flags, uint32_t pitch) in radeon_bo_set_tiling_flags() argument
472 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in radeon_bo_set_tiling_flags()
473 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in radeon_bo_set_tiling_flags()
474 …mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TIL… in radeon_bo_set_tiling_flags()
475 …tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; in radeon_bo_set_tiling_flags()
476 …stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCI… in radeon_bo_set_tiling_flags()
517 bo->tiling_flags = tiling_flags; in radeon_bo_set_tiling_flags()
[all …]
Dradeon_fb.c112 u32 tiling_flags = 0; in radeonfb_create_pinned_object() local
140 tiling_flags = RADEON_TILING_MACRO; in radeonfb_create_pinned_object()
145 tiling_flags |= RADEON_TILING_SWAP_32BIT; in radeonfb_create_pinned_object()
148 tiling_flags |= RADEON_TILING_SWAP_16BIT; in radeonfb_create_pinned_object()
154 if (tiling_flags) { in radeonfb_create_pinned_object()
156 tiling_flags | RADEON_TILING_SURFACE, in radeonfb_create_pinned_object()
Dr300.c687 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
689 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
691 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
756 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
758 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
760 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
841 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r300_packet0_check()
843 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r300_packet0_check()
845 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE) in r300_packet0_check()
Dradeon_object.h135 u32 tiling_flags, u32 pitch);
137 u32 *tiling_flags, u32 *pitch);
Dr200.c218 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
220 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
290 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r200_packet0_check()
292 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r200_packet0_check()
Devergreen_cs.c88 static u32 evergreen_cs_get_aray_mode(u32 tiling_flags) in evergreen_cs_get_aray_mode() argument
90 if (tiling_flags & RADEON_TILING_MACRO) in evergreen_cs_get_aray_mode()
92 else if (tiling_flags & RADEON_TILING_MICRO) in evergreen_cs_get_aray_mode()
1196 ib[idx] |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); in evergreen_cs_check_reg()
1197 track->db_z_info |= Z_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); in evergreen_cs_check_reg()
1198 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { in evergreen_cs_check_reg()
1201 evergreen_tiling_fields(reloc->lobj.tiling_flags, in evergreen_cs_check_reg()
1381 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); in evergreen_cs_check_reg()
1382 track->cb_color_info[tmp] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); in evergreen_cs_check_reg()
1399 ib[idx] |= CB_ARRAY_MODE(evergreen_cs_get_aray_mode(reloc->lobj.tiling_flags)); in evergreen_cs_check_reg()
[all …]
Dradeon_legacy_crtc.c381 uint32_t tiling_flags; in radeon_crtc_do_set_base() local
435 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_do_set_base()
437 if (tiling_flags & RADEON_TILING_MICRO) in radeon_crtc_do_set_base()
455 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
471 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_do_set_base()
Datombios_crtc.c1072 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in dce4_crtc_do_set_base() local
1112 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in dce4_crtc_do_set_base()
1145 if (tiling_flags & RADEON_TILING_MACRO) { in dce4_crtc_do_set_base()
1168 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); in dce4_crtc_do_set_base()
1173 } else if (tiling_flags & RADEON_TILING_MICRO) in dce4_crtc_do_set_base()
1275 uint32_t fb_format, fb_pitch_pixels, tiling_flags; in avivo_crtc_do_set_base() local
1313 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in avivo_crtc_do_set_base()
1351 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
1353 else if (tiling_flags & RADEON_TILING_MICRO) in avivo_crtc_do_set_base()
1356 if (tiling_flags & RADEON_TILING_MACRO) in avivo_crtc_do_set_base()
[all …]
Dr100.c1260 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r100_reloc_pitch_offset()
1262 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { in r100_reloc_pitch_offset()
1604 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1606 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
1685 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r100_packet0_check()
1687 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r100_packet0_check()
3068 uint32_t tiling_flags, uint32_t pitch, in r100_set_surface_reg() argument
3075 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO)) in r100_set_surface_reg()
3078 if (tiling_flags & RADEON_TILING_MACRO) in r100_set_surface_reg()
3081 if (tiling_flags & (RADEON_TILING_MACRO)) in r100_set_surface_reg()
[all …]
Dr600_cs.c1029 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1128 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) { in r600_cs_check_reg()
1131 } else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { in r600_cs_check_reg()
1459 u32 tiling_flags) in r600_check_texture_resource() argument
1481 if (tiling_flags & RADEON_TILING_MACRO) in r600_check_texture_resource()
1483 else if (tiling_flags & RADEON_TILING_MICRO) in r600_check_texture_resource()
1952 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) in r600_packet3_check()
1954 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) in r600_packet3_check()
1970 reloc->lobj.tiling_flags); in r600_packet3_check()
Dradeon_gem.c407 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); in radeon_gem_set_tiling_ioctl()
428 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); in radeon_gem_get_tiling_ioctl()
Dradeon_asic.h90 uint32_t tiling_flags, uint32_t pitch,
325 uint32_t tiling_flags, uint32_t pitch,
Dradeon.h221 extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
350 u32 tiling_flags; member
373 u32 tiling_flags; member
1317 uint32_t tiling_flags, uint32_t pitch,
Dradeon_display.c353 u32 tiling_flags, pitch_pixels; in radeon_crtc_page_flip() local
411 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); in radeon_crtc_page_flip()
419 if (tiling_flags & RADEON_TILING_MACRO) { in radeon_crtc_page_flip()
Devergreen.c914 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, in evergreen_tiling_fields() argument
918 *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; in evergreen_tiling_fields()
919 *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; in evergreen_tiling_fields()
920 …*mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TI… in evergreen_tiling_fields()
921 …*tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MA… in evergreen_tiling_fields()
Dr600.c3189 uint32_t tiling_flags, uint32_t pitch, in r600_set_surface_reg() argument