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Searched refs:tiling_mode (Results 1 – 11 of 11) sorted by relevance

/drivers/gpu/drm/i915/
Di915_gem_tiling.c205 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode) in i915_tiling_ok() argument
210 if (tiling_mode == I915_TILING_NONE) in i915_tiling_ok()
214 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev))) in i915_tiling_ok()
260 i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode) in i915_gem_object_fence_ok() argument
264 if (tiling_mode == I915_TILING_NONE) in i915_gem_object_fence_ok()
278 size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode); in i915_gem_object_fence_ok()
306 args->stride, obj->base.size, args->tiling_mode)) { in i915_gem_set_tiling()
316 if (args->tiling_mode == I915_TILING_NONE) { in i915_gem_set_tiling()
320 if (args->tiling_mode == I915_TILING_X) in i915_gem_set_tiling()
339 args->tiling_mode = I915_TILING_NONE; in i915_gem_set_tiling()
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Dintel_sprite.c105 if (obj->tiling_mode != I915_TILING_NONE) in vlv_update_plane()
123 obj->tiling_mode, in vlv_update_plane()
128 if (obj->tiling_mode != I915_TILING_NONE) in vlv_update_plane()
254 if (obj->tiling_mode != I915_TILING_NONE) in ivb_update_plane()
293 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, in ivb_update_plane()
301 else if (obj->tiling_mode != I915_TILING_NONE) in ivb_update_plane()
442 if (obj->tiling_mode != I915_TILING_NONE) in ilk_update_plane()
466 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, in ilk_update_plane()
470 if (obj->tiling_mode != I915_TILING_NONE) in ilk_update_plane()
636 switch (obj->tiling_mode) { in intel_update_plane()
Di915_gem.c64 if (obj->tiling_mode) in i915_gem_object_fence_lost()
908 obj->tiling_mode == I915_TILING_NONE && in i915_gem_pwrite_ioctl()
1438 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode) in i915_gem_get_gtt_size() argument
1443 tiling_mode == I915_TILING_NONE) in i915_gem_get_gtt_size()
1467 int tiling_mode, bool fenced) in i915_gem_get_gtt_alignment() argument
1474 tiling_mode == I915_TILING_NONE) in i915_gem_get_gtt_alignment()
1481 return i915_gem_get_gtt_size(dev, size, tiling_mode); in i915_gem_get_gtt_alignment()
2553 if (obj->tiling_mode == I915_TILING_Y) in i965_write_fence_reg()
2581 if (obj->tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)) in i915_write_fence_reg()
2591 if (obj->tiling_mode == I915_TILING_Y) in i915_write_fence_reg()
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Di915_gem_execbuffer.c409 obj->tiling_mode != I915_TILING_NONE; in i915_gem_execbuffer_reserve_object()
498 obj->tiling_mode != I915_TILING_NONE; in i915_gem_execbuffer_reserve()
539 obj->tiling_mode != I915_TILING_NONE; in i915_gem_execbuffer_reserve()
Di915_drv.h1163 unsigned int tiling_mode:2; member
1686 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1689 int tiling_mode, bool fenced);
1766 obj->tiling_mode != I915_TILING_NONE; in i915_gem_object_needs_bit17_swizzle()
Dintel_display.c1991 switch (obj->tiling_mode) { in intel_pin_and_fence_fb_obj()
2057 unsigned int tiling_mode, in intel_gen4_compute_page_offset() argument
2061 if (tiling_mode != I915_TILING_NONE) { in intel_gen4_compute_page_offset()
2142 if (obj->tiling_mode != I915_TILING_NONE) in i9xx_update_plane()
2154 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, in i9xx_update_plane()
2234 if (obj->tiling_mode != I915_TILING_NONE) in ironlake_update_plane()
2246 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, in ironlake_update_plane()
6394 if (obj->tiling_mode) { in intel_crtc_cursor_set()
7209 obj->tiling_mode); in intel_gen4_queue_flip()
7250 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); in intel_gen6_queue_flip()
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Dintel_drv.h683 unsigned int tiling_mode,
Dintel_overlay.c1081 if (new_bo->tiling_mode) { in intel_overlay_put_image()
Di915_debugfs.c85 switch (obj->tiling_mode) { in get_tiling_flag()
Di915_irq.c1248 err->tiling = obj->tiling_mode; in capture_bo()
Dintel_pm.c472 if (obj->tiling_mode != I915_TILING_X || in intel_update_fbc()