| /drivers/video/ |
| D | gbefb.c | 40 struct gbe_timing_info timing; member
423 static void gbefb_setup_flatpanel(struct gbe_timing_info *timing) in gbefb_setup_flatpanel() argument
429 (timing->flags & FB_SYNC_HOR_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
431 (timing->flags & FB_SYNC_VERT_HIGH_ACT) ? 0 : 1); in gbefb_setup_flatpanel()
439 timing->pll_m = 4; in gbefb_setup_flatpanel()
440 timing->pll_n = 1; in gbefb_setup_flatpanel()
441 timing->pll_p = 0; in gbefb_setup_flatpanel()
468 struct gbe_timing_info *timing) in compute_gbe_timing() argument
516 if (timing) { in compute_gbe_timing()
517 timing->width = var->xres; in compute_gbe_timing()
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| D | sgivwfb.c | 229 struct dbe_timing_info *timing; in sgivwfb_check_var() local
286 timing = &dbeVTimings[min_mode]; in sgivwfb_check_var()
287 printk(KERN_INFO "sgivwfb: granted dot-clock=%d KHz\n", timing->cfreq); in sgivwfb_check_var()
342 var->pixclock = KHZ2PICOS(timing->cfreq); in sgivwfb_check_var()
343 var->left_margin = timing->htotal - timing->hsync_end; in sgivwfb_check_var()
344 var->right_margin = timing->hsync_start - timing->width; in sgivwfb_check_var()
345 var->upper_margin = timing->vtotal - timing->vsync_end; in sgivwfb_check_var()
346 var->lower_margin = timing->vsync_start - timing->height; in sgivwfb_check_var()
347 var->hsync_len = timing->hsync_end - timing->hsync_start; in sgivwfb_check_var()
348 var->vsync_len = timing->vsync_end - timing->vsync_start; in sgivwfb_check_var()
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| /drivers/gpu/drm/exynos/ |
| D | exynos_drm_connector.c | 36 struct fb_videomode *timing = &panel->timing; in convert_to_display_mode() local
39 mode->clock = timing->pixclock / 1000; in convert_to_display_mode()
40 mode->vrefresh = timing->refresh; in convert_to_display_mode()
42 mode->hdisplay = timing->xres; in convert_to_display_mode()
43 mode->hsync_start = mode->hdisplay + timing->right_margin; in convert_to_display_mode()
44 mode->hsync_end = mode->hsync_start + timing->hsync_len; in convert_to_display_mode()
45 mode->htotal = mode->hsync_end + timing->left_margin; in convert_to_display_mode()
47 mode->vdisplay = timing->yres; in convert_to_display_mode()
48 mode->vsync_start = mode->vdisplay + timing->lower_margin; in convert_to_display_mode()
49 mode->vsync_end = mode->vsync_start + timing->vsync_len; in convert_to_display_mode()
[all …]
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| D | exynos_drm_fimd.c | 156 static int fimd_check_timing(struct device *dev, void *timing) in fimd_check_timing() argument
240 struct fb_videomode *timing = &panel->timing; in fimd_commit() local
255 val = VIDTCON0_VBPD(timing->upper_margin - 1) | in fimd_commit()
256 VIDTCON0_VFPD(timing->lower_margin - 1) | in fimd_commit()
257 VIDTCON0_VSPW(timing->vsync_len - 1); in fimd_commit()
261 val = VIDTCON1_HBPD(timing->left_margin - 1) | in fimd_commit()
262 VIDTCON1_HFPD(timing->right_margin - 1) | in fimd_commit()
263 VIDTCON1_HSPW(timing->hsync_len - 1); in fimd_commit()
267 val = VIDTCON2_LINEVAL(timing->yres - 1) | in fimd_commit()
268 VIDTCON2_HOZVAL(timing->xres - 1) | in fimd_commit()
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| /drivers/video/via/ |
| D | via_modesetting.c | 33 void via_set_primary_timing(const struct via_display_timing *timing) in via_set_primary_timing() argument
37 raw.hor_total = timing->hor_total / 8 - 5; in via_set_primary_timing()
38 raw.hor_addr = timing->hor_addr / 8 - 1; in via_set_primary_timing()
39 raw.hor_blank_start = timing->hor_blank_start / 8 - 1; in via_set_primary_timing()
40 raw.hor_blank_end = timing->hor_blank_end / 8 - 1; in via_set_primary_timing()
41 raw.hor_sync_start = timing->hor_sync_start / 8; in via_set_primary_timing()
42 raw.hor_sync_end = timing->hor_sync_end / 8; in via_set_primary_timing()
43 raw.ver_total = timing->ver_total - 2; in via_set_primary_timing()
44 raw.ver_addr = timing->ver_addr - 1; in via_set_primary_timing()
45 raw.ver_blank_start = timing->ver_blank_start - 1; in via_set_primary_timing()
[all …]
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| /drivers/media/i2c/ |
| D | bt819.c | 75 struct timing { struct
85 static struct timing timing_data[] = { argument
190 struct timing *timing = &timing_data[(decoder->norm & V4L2_STD_525_60) ? 1 : 0]; in bt819_init() local
193 (((timing->vdelay >> 8) & 0x03) << 6) | in bt819_init()
194 (((timing->vactive >> 8) & 0x03) << 4) | in bt819_init()
195 (((timing->hdelay >> 8) & 0x03) << 2) | in bt819_init()
196 ((timing->hactive >> 8) & 0x03); in bt819_init()
197 init[0x04 * 2 - 1] = timing->vdelay & 0xff; in bt819_init()
198 init[0x05 * 2 - 1] = timing->vactive & 0xff; in bt819_init()
199 init[0x06 * 2 - 1] = timing->hdelay & 0xff; in bt819_init()
[all …]
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| /drivers/ide/ |
| D | triflex.c | 41 u16 timing = 0; in triflex_set_mode() local
48 timing = 0x0103; in triflex_set_mode()
51 timing = 0x0203; in triflex_set_mode()
54 timing = 0x0808; in triflex_set_mode()
59 timing = 0x0f0f; in triflex_set_mode()
62 timing = 0x0202; in triflex_set_mode()
65 timing = 0x0204; in triflex_set_mode()
68 timing = 0x0404; in triflex_set_mode()
71 timing = 0x0508; in triflex_set_mode()
74 timing = 0x0808; in triflex_set_mode()
[all …]
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| D | amd74xx.c | 51 struct ide_timing *timing) in amd_set_speed() argument
56 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); in amd_set_speed()
60 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); in amd_set_speed()
63 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); in amd_set_speed()
66 case ATA_UDMA2: t = timing->udma ? (0xc0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; in amd_set_speed()
67 …case ATA_UDMA4: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 2, 10)]) : 0x03; b… in amd_set_speed()
68 …case ATA_UDMA5: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 10)]) : 0x03; b… in amd_set_speed()
69 …case ATA_UDMA6: t = timing->udma ? (0xc0 | amd_cyc2udma[clamp_val(timing->udma, 1, 15)]) : 0x03; b… in amd_set_speed()
73 if (timing->udma) in amd_set_speed()
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| D | ht6560b.c | 120 u8 select, timing; in ht6560b_dev_select() local
125 timing = HT_TIMING(drive); in ht6560b_dev_select()
135 if (select != current_select || timing != current_timing) { in ht6560b_dev_select()
137 current_timing = timing; in ht6560b_dev_select()
146 outb(timing, hwif->io_ports.device_addr); in ht6560b_dev_select()
150 drive->name, select, timing); in ht6560b_dev_select()
285 u8 timing; in ht6560b_set_pio_mode() local
294 timing = ht_pio2timings(drive, pio); in ht6560b_set_pio_mode()
299 config |= timing; in ht6560b_set_pio_mode()
304 printk("ht6560b: drive %s tuned to pio mode %#x timing=%#x\n", drive->name, pio, timing); in ht6560b_set_pio_mode()
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| D | via82cxxx.c | 125 static void via_set_speed(ide_hwif_t *hwif, u8 dn, struct ide_timing *timing) in via_set_speed() argument
134 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(timing->setup, 1, 4) - 1) << ((3 - dn) << 1)); in via_set_speed()
139 ((clamp_val(timing->act8b, 1, 16) - 1) << 4) | (clamp_val(timing->rec8b, 1, 16) - 1)); in via_set_speed()
142 ((clamp_val(timing->active, 1, 16) - 1) << 4) | (clamp_val(timing->recover, 1, 16) - 1)); in via_set_speed()
145 case ATA_UDMA2: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 5) - 2)) : 0x03; break; in via_set_speed()
146 case ATA_UDMA4: t = timing->udma ? (0xe8 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x0f; break; in via_set_speed()
147 case ATA_UDMA5: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; in via_set_speed()
148 case ATA_UDMA6: t = timing->udma ? (0xe0 | (clamp_val(timing->udma, 2, 9) - 2)) : 0x07; break; in via_set_speed()
160 if (timing->udma) { in via_set_speed()
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| /drivers/char/ |
| D | bfin-otp.c | 90 u32 tp1, tp2, tp3, timing; in bfin_otp_init_timing() local
95 timing = tp1 | tp2 | tp3; in bfin_otp_init_timing()
96 if (bfrom_OtpCommand(OTP_INIT, timing)) in bfin_otp_init_timing()
99 return timing; in bfin_otp_init_timing()
107 static void bfin_otp_deinit_timing(u32 timing) in bfin_otp_deinit_timing() argument
111 bfrom_OtpCommand(OTP_INIT, timing & ~(-1 << 15)); in bfin_otp_deinit_timing()
123 u32 timing, page, base_flags, flags, ret; in bfin_otp_write() local
137 timing = bfin_otp_init_timing(); in bfin_otp_write()
138 if (timing == 0) { in bfin_otp_write()
167 bfin_otp_deinit_timing(timing); in bfin_otp_write()
[all …]
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| /drivers/ata/ |
| D | pata_triflex.c | 89 u32 timing = 0; in triflex_load_timing() local
101 timing = 0x0103;break; in triflex_load_timing()
103 timing = 0x0203;break; in triflex_load_timing()
105 timing = 0x0808;break; in triflex_load_timing()
109 timing = 0x0F0F;break; in triflex_load_timing()
111 timing = 0x0202;break; in triflex_load_timing()
113 timing = 0x0204;break; in triflex_load_timing()
115 timing = 0x0404;break; in triflex_load_timing()
117 timing = 0x0508;break; in triflex_load_timing()
119 timing = 0x0808;break; in triflex_load_timing()
[all …]
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| D | pata_sis.c | 342 u16 timing; in sis_old_set_dmamode() local
347 pci_read_config_word(pdev, drive_pci, &timing); in sis_old_set_dmamode()
352 timing &= ~0x870F; in sis_old_set_dmamode()
353 timing |= mwdma_bits[speed]; in sis_old_set_dmamode()
357 timing &= ~0x6000; in sis_old_set_dmamode()
358 timing |= udma_bits[speed]; in sis_old_set_dmamode()
360 pci_write_config_word(pdev, drive_pci, timing); in sis_old_set_dmamode()
381 u16 timing; in sis_66_set_dmamode() local
387 pci_read_config_word(pdev, drive_pci, &timing); in sis_66_set_dmamode()
392 timing &= ~0x870F; in sis_66_set_dmamode()
[all …]
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| D | pata_cs5530.c | 89 u32 tuning, timing = 0; in cs5530_set_dmamode() local
97 timing = 0x00921250;break; in cs5530_set_dmamode()
99 timing = 0x00911140;break; in cs5530_set_dmamode()
101 timing = 0x00911030;break; in cs5530_set_dmamode()
103 timing = 0x00077771;break; in cs5530_set_dmamode()
105 timing = 0x00012121;break; in cs5530_set_dmamode()
107 timing = 0x00002020;break; in cs5530_set_dmamode()
112 timing |= (tuning & 0x80000000UL); in cs5530_set_dmamode()
114 iowrite32(timing, base + 0x04); in cs5530_set_dmamode()
116 if (timing & 0x00100000) in cs5530_set_dmamode()
[all …]
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| D | pata_cmd640.c | 54 struct cmd640_reg *timing = ap->private_data; in cmd640_set_piomode() local
116 timing->reg58[adev->devno] = (t.active << 4) | t.recover; in cmd640_set_piomode()
134 struct cmd640_reg *timing = ap->private_data; in cmd640_qc_issue() local
136 if (ap->port_no != 0 && adev->devno != timing->last) { in cmd640_qc_issue()
137 pci_write_config_byte(pdev, DRWTIM23, timing->reg58[adev->devno]); in cmd640_qc_issue()
138 timing->last = adev->devno; in cmd640_qc_issue()
154 struct cmd640_reg *timing; in cmd640_port_start() local
156 timing = devm_kzalloc(&pdev->dev, sizeof(struct cmd640_reg), GFP_KERNEL); in cmd640_port_start()
157 if (timing == NULL) in cmd640_port_start()
159 timing->last = -1; /* Force a load */ in cmd640_port_start()
[all …]
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| D | pata_at32.c | 96 struct smc_timing timing; in pata_at32_setup_timing() local
101 memset(&timing, 0, sizeof(struct smc_timing)); in pata_at32_setup_timing()
104 timing.read_cycle = ata->cyc8b; in pata_at32_setup_timing()
107 timing.nrd_setup = ata->setup; in pata_at32_setup_timing()
108 timing.nrd_pulse = ata->act8b; in pata_at32_setup_timing()
109 timing.nrd_recover = ata->rec8b; in pata_at32_setup_timing()
112 smc_set_timing(smc, &timing); in pata_at32_setup_timing()
152 struct ata_timing timing; in pata_at32_set_piomode() local
158 ret = ata_timing_compute(adev, adev->pio_mode, &timing, 1000, 0); in pata_at32_set_piomode()
165 ret = pata_at32_setup_timing(ap->dev, info, &timing); in pata_at32_set_piomode()
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| D | pata_legacy.c | 99 unsigned long timing; member
656 u8 timing; in qdi65x0_set_piomode() local
668 timing = (recovery << 4) | active | 0x08; in qdi65x0_set_piomode()
669 ld_qdi->clock[adev->devno] = timing; in qdi65x0_set_piomode()
672 outb(timing, ld_qdi->timing + 2 * adev->devno); in qdi65x0_set_piomode()
674 outb(timing, ld_qdi->timing + 2 * ap->port_no); in qdi65x0_set_piomode()
678 outb(0x5F, (ld_qdi->timing & 0xFFF0) + 3); in qdi65x0_set_piomode()
698 outb(ld_qdi->clock[adev->devno], ld_qdi->timing + in qdi_qc_issue()
738 ld->timing = lp->private; in qdi_port()
792 int timing = 0x88 + (ap->port_no * 4) + (adev->devno * 2); in winbond_set_piomode() local
[all …]
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| D | pata_sl82c105.c | 85 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); in sl82c105_configure_piomode() local
87 pci_write_config_word(pdev, timing, pio_timing[pio]); in sl82c105_configure_piomode()
89 pci_read_config_word(pdev, timing, &dummy); in sl82c105_configure_piomode()
122 int timing = 0x44 + (8 * ap->port_no) + (4 * adev->devno); in sl82c105_configure_dmamode() local
125 pci_write_config_word(pdev, timing, dma_timing[dma]); in sl82c105_configure_dmamode()
127 pci_read_config_word(pdev, timing, &dummy); in sl82c105_configure_dmamode()
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| /drivers/pcmcia/ |
| D | sa11xx_base.c | 81 struct soc_pcmcia_timing timing; in sa1100_pcmcia_set_mecr() local
86 soc_common_pcmcia_get_timing(skt, &timing); in sa1100_pcmcia_set_mecr()
88 bs_io = skt->ops->get_timing(skt, cpu_clock, timing.io); in sa1100_pcmcia_set_mecr()
89 bs_mem = skt->ops->get_timing(skt, cpu_clock, timing.mem); in sa1100_pcmcia_set_mecr()
90 bs_attr = skt->ops->get_timing(skt, cpu_clock, timing.attr); in sa1100_pcmcia_set_mecr()
147 struct soc_pcmcia_timing timing; in sa1100_pcmcia_show_timing() local
152 soc_common_pcmcia_get_timing(skt, &timing); in sa1100_pcmcia_show_timing()
154 p+=sprintf(p, "I/O : %u (%u)\n", timing.io, in sa1100_pcmcia_show_timing()
157 p+=sprintf(p, "attribute: %u (%u)\n", timing.attr, in sa1100_pcmcia_show_timing()
160 p+=sprintf(p, "common : %u (%u)\n", timing.mem, in sa1100_pcmcia_show_timing()
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| /drivers/mmc/host/ |
| D | dw_mmc-exynos.c | 122 if (ios->timing == MMC_TIMING_UHS_DDR50) in dw_mci_exynos_set_ios()
132 u32 timing[2]; in dw_mci_exynos_parse_dt() local
140 "samsung,dw-mshc-sdr-timing", timing, 2); in dw_mci_exynos_parse_dt()
144 priv->sdr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); in dw_mci_exynos_parse_dt()
147 "samsung,dw-mshc-ddr-timing", timing, 2); in dw_mci_exynos_parse_dt()
151 priv->ddr_timing = SDMMC_CLKSEL_TIMING(timing[0], timing[1], div); in dw_mci_exynos_parse_dt()
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| /drivers/mtd/nand/ |
| D | cafe_nand.c | 90 static int timing[3]; variable
91 module_param_array(timing, int, &numtimings, 0644);
698 timing[0], timing[1], timing[2]); in cafe_nand_probe()
700 timing[0] = cafe_readl(cafe, NAND_TIMING1); in cafe_nand_probe()
701 timing[1] = cafe_readl(cafe, NAND_TIMING2); in cafe_nand_probe()
702 timing[2] = cafe_readl(cafe, NAND_TIMING3); in cafe_nand_probe()
704 if (timing[0] | timing[1] | timing[2]) { in cafe_nand_probe()
706 timing[0], timing[1], timing[2]); in cafe_nand_probe()
709 timing[0] = timing[1] = timing[2] = 0xffffffff; in cafe_nand_probe()
717 cafe_writel(cafe, timing[0], NAND_TIMING1); in cafe_nand_probe()
[all …]
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| /drivers/gpu/drm/nouveau/ |
| D | nouveau_perf.c | 169 u8 *perf, *timing = NULL; in nouveau_perf_timing() local
186 timing = ROMPTR(dev, P.data[4]); in nouveau_perf_timing()
189 timing = ROMPTR(dev, P.data[8]); in nouveau_perf_timing()
192 if (timing && timing[0] == 0x10) { in nouveau_perf_timing()
194 if (ramcfg && ramcfg[1] < timing[2]) { in nouveau_perf_timing()
195 *ver = timing[0]; in nouveau_perf_timing()
196 *len = timing[3]; in nouveau_perf_timing()
197 return timing + timing[1] + (ramcfg[1] * timing[3]); in nouveau_perf_timing()
393 &perflvl->timing); in nouveau_perf_init()
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| /drivers/media/platform/omap3isp/ |
| D | ispcsi2.c | 369 struct isp_csi2_timing_cfg *timing) in csi2_timing_config() argument
375 if (timing->force_rx_mode) in csi2_timing_config()
376 reg |= ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum); in csi2_timing_config()
378 reg &= ~ISPCSI2_TIMING_FORCE_RX_MODE_IO(timing->ionum); in csi2_timing_config()
380 if (timing->stop_state_16x) in csi2_timing_config()
381 reg |= ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum); in csi2_timing_config()
383 reg &= ~ISPCSI2_TIMING_STOP_STATE_X16_IO(timing->ionum); in csi2_timing_config()
385 if (timing->stop_state_4x) in csi2_timing_config()
386 reg |= ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum); in csi2_timing_config()
388 reg &= ~ISPCSI2_TIMING_STOP_STATE_X4_IO(timing->ionum); in csi2_timing_config()
[all …]
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| /drivers/video/exynos/ |
| D | exynos_mipi_dsi_common.c | 714 struct fb_videomode *timing; in exynos_mipi_dsi_set_display_mode() local
717 timing = (struct fb_videomode *)dsim_pd->lcd_panel_info; in exynos_mipi_dsi_set_display_mode()
724 timing->lower_margin, in exynos_mipi_dsi_set_display_mode()
725 timing->upper_margin); in exynos_mipi_dsi_set_display_mode()
727 timing->right_margin, in exynos_mipi_dsi_set_display_mode()
728 timing->left_margin); in exynos_mipi_dsi_set_display_mode()
730 timing->vsync_len, in exynos_mipi_dsi_set_display_mode()
731 timing->hsync_len); in exynos_mipi_dsi_set_display_mode()
735 exynos_mipi_dsi_set_main_disp_resol(dsim, timing->xres, in exynos_mipi_dsi_set_display_mode()
736 timing->yres); in exynos_mipi_dsi_set_display_mode()
[all …]
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| /drivers/gpu/drm/ |
| D | drm_edid.c | 1367 typedef void detailed_cb(struct detailed_timing *timing, void *closure);
1690 struct detailed_timing *timing, in drm_mode_detailed() argument
1694 struct detailed_pixel_timing *pt = &timing->data.pixel_data; in drm_mode_detailed()
1736 timing->pixel_clock = cpu_to_le16(1088); in drm_mode_detailed()
1738 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; in drm_mode_detailed()
1839 struct detailed_timing *timing) in mode_in_range() argument
1842 u8 *t = (u8 *)timing; in mode_in_range()
1885 struct detailed_timing *timing) in drm_dmt_modes_for_range() argument
1892 if (mode_in_range(drm_dmt_modes + i, edid, timing) && in drm_dmt_modes_for_range()
1920 struct detailed_timing *timing) in drm_gtf_modes_for_range() argument
[all …]
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