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Searched refs:train_set (Results 1 – 4 of 4) sorted by relevance

/drivers/gpu/drm/radeon/
Datombios_dp.c297 u8 train_set[4]) in dp_get_adjust_train()
329 train_set[lane] = v | p; in dp_get_adjust_train()
579 u8 train_set[4]; member
590 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph()
594 dp_info->train_set, dp_info->dp_lane_count, 0); in radeon_dp_update_vs_emph()
710 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
733 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
741 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr()
750 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
753 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_cr()
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/drivers/gpu/drm/i915/
Dintel_dp.c1533 intel_dp->train_set[lane] = v | p; in intel_get_adjust_train()
1537 intel_gen4_signal_levels(uint8_t train_set) in intel_gen4_signal_levels() argument
1541 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in intel_gen4_signal_levels()
1556 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in intel_gen4_signal_levels()
1576 intel_gen6_edp_signal_levels(uint8_t train_set) in intel_gen6_edp_signal_levels() argument
1578 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_gen6_edp_signal_levels()
1604 intel_gen7_edp_signal_levels(uint8_t train_set) in intel_gen7_edp_signal_levels() argument
1606 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_gen7_edp_signal_levels()
1635 intel_hsw_signal_levels(uint8_t train_set) in intel_hsw_signal_levels() argument
1637 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_hsw_signal_levels()
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Dintel_drv.h415 uint8_t train_set[4]; member
/drivers/gpu/drm/gma500/
Dcdv_intel_dp.c74 uint8_t train_set[4]; member
1132 intel_dp->train_set[lane] = v | p; in cdv_intel_get_adjust_train()
1223 intel_dp->train_set, in cdv_intel_dplink_set_level()
1228 intel_dp->train_set[0], intel_dp->lane_count); in cdv_intel_dplink_set_level()
1328 memset(intel_dp->train_set, 0, 4); in cdv_intel_dp_start_link_train()
1340 intel_dp->train_set[0], in cdv_intel_dp_start_link_train()
1347 cdv_intel_dp_set_vswing_premph(encoder, intel_dp->train_set[0]); in cdv_intel_dp_start_link_train()
1368 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in cdv_intel_dp_start_link_train()
1374 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in cdv_intel_dp_start_link_train()
1380 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in cdv_intel_dp_start_link_train()
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