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Searched refs:vsw (Results 1 – 25 of 36) sorted by relevance

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/drivers/video/omap2/displays/
Dpanel-generic-dpi.c68 .vsw = 11,
95 .vsw = 1,
123 .vsw = 2,
150 .vsw = 10,
176 .vsw = 2,
203 .vsw = 10,
230 .vsw = 3,
257 .vsw = 1,
282 .vsw = 1,
307 .vsw = 3,
[all …]
Dpanel-sharp-ls037v7dw01.c41 .vsw = 1,
Dpanel-nec-nl8048hl11-01b.c74 .vsw = 1,
Dpanel-lgphilips-lb035q02.c42 .vsw = 2,
Dpanel-tfp410.c40 .vsw = 4,
/drivers/video/
Dcarminefb.c66 u32 vsw; member
109 .vsw = 2,
121 .vsw = 2,
370 u32 hdp, vdp, htp, hsp, hsw, vtr, vsp, vsw; in set_display_parameters() local
383 vsw = par->res->vsw - 1; in set_display_parameters()
390 (vsw << CARMINE_DISP_VSW_SHIFT) | in set_display_parameters()
/drivers/gpu/drm/nouveau/core/engine/disp/
Dpiornv50.c79 int head, int lane, int vsw, int pre) in nv50_pior_dp_drv_ctl() argument
87 ret = port->func->drv_ctl(port, lane, vsw, pre); in nv50_pior_dp_drv_ctl()
/drivers/gpu/drm/tilcdc/
Dtilcdc_crtc.c241 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw; in tilcdc_crtc_mode_set() local
283 vsw = mode->vsync_end - mode->vsync_start; in tilcdc_crtc_mode_set()
286 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw); in tilcdc_crtc_mode_set()
310 ((vsw & 0x3f) << 10); in tilcdc_crtc_mode_set()
/drivers/video/omap/
Dhwa742.c792 int hsw, vsw; in setup_tearsync() local
799 vsw = hwa742_read_reg(HWA742_VS_W_REG); in setup_tearsync()
801 vs_pol_inv = !(vsw & 0x80); in setup_tearsync()
803 vsw = vsw & 0x3f; in setup_tearsync()
859 vs = vsw; in setup_tearsync()
Dlcd_htcherald.c74 .vsw = 3,
Dlcd_inn1510.c68 .vsw = 1,
Dlcd_palmte.c66 .vsw = 1,
Dlcd_palmz71.c67 .vsw = 1,
Dlcd_palmtt.c72 .vsw = 1,
Dlcd_osk.c89 .vsw = 1,
Dlcd_inn1610.c89 .vsw = 1,
Dlcd_h3.c83 .vsw = 1,
Dlcd_ams_delta.c156 .vsw = 1,
Domapfb.h83 int vsw; /* Vertical synchronization member
/drivers/gpu/drm/omapdrm/
Domap_connector.c49 mode->vsync_end = mode->vsync_start + timings->vsw; in copy_timings_omap_to_drm()
80 timings->vsw = mode->vsync_end - mode->vsync_start; in copy_timings_drm_to_omap()
/drivers/video/omap2/dss/
Ddisplay-sysfs.c110 t.y_res, t.vfp, t.vbp, t.vsw); in display_timings_show()
136 &t.y_res, &t.vfp, &t.vbp, &t.vsw) != 9) in display_timings_store()
Dvenc_panel.c96 .vsw = 5, in venc_panel_probe()
Dti_hdmi_4xxx_ip.c693 timings->vsw = 0; in hdmi_wp_init()
725 timings->vsw = param->timings.vsw; in hdmi_wp_video_init_format()
773 timing_v |= FLD_VAL(timings->vsw, 7, 0); in hdmi_wp_video_config_timing()
Ddispc.c2832 int vsw, int vfp, int vbp) in _dispc_lcd_timings_ok() argument
2837 vsw < 1 || vsw > dispc.feat->sw_max || in _dispc_lcd_timings_ok()
2864 timings->hbp, timings->vsw, timings->vfp, in dispc_mgr_timings_ok()
2872 int hfp, int hbp, int vsw, int vfp, int vbp, in _dispc_mgr_set_lcd_timings() argument
2886 timing_v = FLD_VAL(vsw-1, dispc.feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
2948 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw, in dispc_mgr_set_timings()
2953 ytot = t.y_res + t.vfp + t.vsw + t.vbp; in dispc_mgr_set_timings()
2960 t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp); in dispc_mgr_set_timings()
Dhdmi_panel.c52 .vsw = 2, in hdmi_panel_probe()

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